operands.isa (2954:6839b9e49575) operands.isa (2962:4f3ee6fa65fa)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 69 unchanged lines hidden (view full) ---

78 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
79 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
80 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
81 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
82 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
83 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
84 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
85
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 69 unchanged lines hidden (view full) ---

78 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
79 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
80 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
81 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
82 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
83 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
84 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
85
86 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55)
86 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
87 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)
87
88}};
88
89}};