operands.isa (2632:1bb2f91485ea) operands.isa (2646:c5f20661d9f3)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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58 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
59 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
60 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
61 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
62 'R0': ('IntReg', 'udw', '0', None, 6),
63 'R1': ('IntReg', 'udw', '1', None, 7),
64 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
65 'R16': ('IntReg', 'udw', '16', None, 9),
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 49 unchanged lines hidden (view full) ---

58 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
59 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
60 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
61 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
62 'R0': ('IntReg', 'udw', '0', None, 6),
63 'R1': ('IntReg', 'udw', '1', None, 7),
64 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
65 'R16': ('IntReg', 'udw', '16', None, 9),
66
66 # Control registers
67 # Control registers
67 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
68 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
69 'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
70 'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
71 'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
72 'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
73 'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
74 'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
75 'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
76 'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
77 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
78 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
68 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
79 'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
80 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
81 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
82 #'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
83 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
69 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
84 'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
85 'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
86 'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
87 'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
88 'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
89 'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
90 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
91 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
92 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
93 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
94 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
70 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
71
72 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
73 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 28),
74 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28),
75 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
95 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
76 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
96 #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
97 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
98 'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
99 'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
77
78 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
100 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
101 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
79 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
80 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
102 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
103 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
81 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
82 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
104 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
83 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
105 'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
106 'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
107 'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41),
108 'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
109 'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
110 'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
111 'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
112 'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
113 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
114 'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
115 'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
116 'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
117 'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
118 'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
119 'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
120 'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
121 'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
122 'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
123 'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
124 'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
125 'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
126 'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
127 'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
128 'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
129 'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
130 'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
131 'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
132 'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
133 'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
134 'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
135 'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
136 'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
137 'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
138 'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
139 'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
140 'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
141 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
142 'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
143 'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
144 'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
84 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 12),
85
86 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47)
87
145}};
88}};