1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 37 unchanged lines hidden (view full) --- 46 # Int regs default to unsigned, but code should not count on this. 47 # For clarity, descriptions that depend on unsigned behavior should 48 # explicitly specify '.uq'. 49 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 50 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 51 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 52 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 53 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), |
54 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10), 55 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 56 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 57 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 58 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 59 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), |
60 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 61 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 62 'R0': ('IntReg', 'udw', '0', None, 6), 63 'R1': ('IntReg', 'udw', '1', None, 7), 64 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 65 'R16': ('IntReg', 'udw', '16', None, 9), 66 67 # Control registers |
68 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 69 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 70 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), |
71 |
72 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 73 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 74 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 75 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 76 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), |
77 |
78 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 79 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 80 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 81 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 82 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 83 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 84 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), |
85 |
86 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55) |
87 88}}; |