83,84d82
< #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
< #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
93a92,101
> 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
> 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
> 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
> 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
> 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
> 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
> 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
> 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
> 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
> 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
95,100c103,118
< 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
< 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
< 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
< 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
< 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
< 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
---
> 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
> 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
> 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
> 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
> 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
> 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
> 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
> 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
> 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
> 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
> 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
> 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
> 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
> 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
> 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
> 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
102,108c120,125
< 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
< 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
< 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
< 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
< 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
< 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
< 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
---
> 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
> 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
> 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
> 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
> 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
> 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
110,111c127
< 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
< 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
---
> 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),