59d58
<
61,75c60,67
< # The Rd from the previous window
< 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
< # The Rd from the next window
< 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
< # The low (even) register of a two register pair
< 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
< # The high (odd) register of a two register pair
< 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
< 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
< 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
< # A microcode register. Right now, this is the only one.
< 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
< # Because double and quad precision register numbers are decoded
< # differently, they get different operands. The single precision versions
< # have an s post pended to their name.
---
> # For microcoded twin load instructions, RdTwin appears in the "code"
> # for the instruction and is replaced by RdLow or RdHigh by the format
> # before it's processed by the iop.
> 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
> 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
> 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
> 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
> 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
94d85
< # Registers which are used explicitly in instructions
101,104c92,93
< # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
< # 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
< 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
< 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
---
> 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
> 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
126,136c115,120
< 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
< # 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
< # 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
< # 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
< # 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
< # 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
< 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
< 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
< 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
< 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
< 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
---
> 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
> 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
> 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
> 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
> 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
> 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
<
61,75c60,67
< # The Rd from the previous window
< 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
< # The Rd from the next window
< 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
< # The low (even) register of a two register pair
< 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
< # The high (odd) register of a two register pair
< 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
< 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
< 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
< # A microcode register. Right now, this is the only one.
< 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
< # Because double and quad precision register numbers are decoded
< # differently, they get different operands. The single precision versions
< # have an s post pended to their name.
---
> # For microcoded twin load instructions, RdTwin appears in the "code"
> # for the instruction and is replaced by RdLow or RdHigh by the format
> # before it's processed by the iop.
> 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
> 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
> 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
> 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
> 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
94d85
< # Registers which are used explicitly in instructions
101,104c92,93
< # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
< # 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
< 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
< 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
---
> 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
> 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
126,136c115,120
< 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
< # 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
< # 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
< # 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
< # 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
< # 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
< 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
< 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
< 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
< 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
< 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
---
> 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
> 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
> 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
> 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
> 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
> 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),