80d79
< 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
110c109,111
< 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)
---
> 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
> # Mem gets a large number so it's always last
> 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)