44a45,54
> output header {{
> // A function to "decompress" double and quad floating point
> // register numbers stuffed into 5 bit fields. These have their
> // MSB put in the LSB position but are otherwise normal.
> static inline unsigned int dfpr(unsigned int regNum)
> {
> return regNum | ((regNum & 1) << 5);
> }
> }};
>
54,64c64,79
< 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
< 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
< 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
< 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
< 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
< 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
< 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
< 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
< 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
< 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
< 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
---
> 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
> 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
> # Each Frd_N refers to the Nth double precision register from Frd.
> # Note that this adds twice N to the register number.
> 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
> 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
> 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
> 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
> 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
> 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
> 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
> 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
> 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
> 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
> 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
> 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),