Cross Reference: /gem5/src/arch/sparc/isa/operands.isa

Deleted Added

sdiff udiff text old ( 8829:d21889bface6 ) new ( 12386:2bf5fb25a5f1 )

full compact

operands.isa (8829:d21889bface6)	operands.isa (12386:2bf5fb25a5f1)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : 'int8_t', 33 'ub' : 'uint8_t', 34 'shw' : 'int16_t', 35 'uhw' : 'uint16_t', 36 'sw' : 'int32_t', 37 'uw' : 'uint32_t', 38 'sdw' : 'int64_t', 39 'udw' : 'uint64_t',	1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : 'int8_t', 33 'ub' : 'uint8_t', 34 'shw' : 'int16_t', 35 'uhw' : 'uint16_t', 36 'sw' : 'int32_t', 37 'uw' : 'uint32_t', 38 'sdw' : 'int64_t', 39 'udw' : 'uint64_t',
40 'tudw' : 'Twin64_t', 41 'tuw' : 'Twin32_t',	40 'tudw' : 'std::array<uint64_t, 2>', 41 'tuw' : 'std::array<uint32_t, 2>',
42 'sf' : 'float', 43 'df' : 'double', 44 45 'pstate' : 'PSTATE', 46 'hpstate' : 'HPSTATE' 47}}; 48 49output header {{ 50 // A function to "decompress" double and quad floating point 51 // register numbers stuffed into 5 bit fields. These have their 52 // MSB put in the LSB position but are otherwise normal. 53 static inline unsigned int 54 dfpr(unsigned int regNum) 55 { 56 return (regNum & (~1)) \| ((regNum & 1) << 5); 57 } 58 59 static inline unsigned int 60 dfprl(unsigned int regNum) 61 { 62 return dfpr(regNum) & (~0x1); 63 } 64 65 static inline unsigned int 66 dfprh(unsigned int regNum) 67 { 68 return dfpr(regNum) \| 0x1; 69 } 70}}; 71 72def operands {{ 73 # Int regs default to unsigned, but code should not count on this. 74 # For clarity, descriptions that depend on unsigned behavior should 75 # explicitly specify '.uq'. 76 77 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 78 # The Rd from the previous window 79 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 80 # The Rd from the next window 81 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 82 # For microcoded twin load instructions, RdTwin appears in the "code" 83 # for the instruction is replaced by RdLow or RdHigh by the format 84 # before it's processed by the iop. 85 # The low (even) register of a two register pair 86 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 87 # The high (odd) register of a two register pair 88 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 5), 89 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 90 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 91 # A microcode register. Right now, this is the only one. 92 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 93 # Because double and quad precision register numbers are decoded 94 # differently, they get different operands. The single precision versions 95 # have an s post pended to their name. 96 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 97 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 98 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 99 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 100 # Each Frd_N refers to the Nth double precision register from Frd. 101 # Note that this adds twice N to the register number. 102 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 103 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 104 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 105 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 106 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 107 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 108 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 109 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 110 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 111 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 112 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 113 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 114 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 115 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 116 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 117 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 118 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 119 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 120 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 121 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 122 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 123 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 124 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 125 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 126 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 127 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 128 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 129 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 130 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 131 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 132 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 133 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 134 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 135 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 136 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 137 # Registers which are used explicitly in instructions 138 'R0': ('IntReg', 'udw', '0', None, 6), 139 'R1': ('IntReg', 'udw', '1', None, 7), 140 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 141 'R16': ('IntReg', 'udw', '16', None, 9), 142 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 143 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 144 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 145 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 146 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 147 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 148 149 # Control registers 150# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 151# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 152 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 153 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 154 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 155 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 156 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 157 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 158# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 159 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 160 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 161 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 162 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 163 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 164 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 165 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 166 167 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 168 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 169 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 170 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 171 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 172 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 173 'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59), 174 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 175 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 176 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 177# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 178# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 179# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 180# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 181# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 182 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 183 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 184 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 185 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 186 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 187 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 188 189 'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69), 190 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 191 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 192 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 193 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 194 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 195 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 196 197 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 198 # Mem gets a large number so it's always last 199 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 200 201}};	42 'sf' : 'float', 43 'df' : 'double', 44 45 'pstate' : 'PSTATE', 46 'hpstate' : 'HPSTATE' 47}}; 48 49output header {{ 50 // A function to "decompress" double and quad floating point 51 // register numbers stuffed into 5 bit fields. These have their 52 // MSB put in the LSB position but are otherwise normal. 53 static inline unsigned int 54 dfpr(unsigned int regNum) 55 { 56 return (regNum & (~1)) \| ((regNum & 1) << 5); 57 } 58 59 static inline unsigned int 60 dfprl(unsigned int regNum) 61 { 62 return dfpr(regNum) & (~0x1); 63 } 64 65 static inline unsigned int 66 dfprh(unsigned int regNum) 67 { 68 return dfpr(regNum) \| 0x1; 69 } 70}}; 71 72def operands {{ 73 # Int regs default to unsigned, but code should not count on this. 74 # For clarity, descriptions that depend on unsigned behavior should 75 # explicitly specify '.uq'. 76 77 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 78 # The Rd from the previous window 79 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 80 # The Rd from the next window 81 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 82 # For microcoded twin load instructions, RdTwin appears in the "code" 83 # for the instruction is replaced by RdLow or RdHigh by the format 84 # before it's processed by the iop. 85 # The low (even) register of a two register pair 86 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 87 # The high (odd) register of a two register pair 88 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 5), 89 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 90 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 91 # A microcode register. Right now, this is the only one. 92 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 93 # Because double and quad precision register numbers are decoded 94 # differently, they get different operands. The single precision versions 95 # have an s post pended to their name. 96 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 97 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 98 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 99 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 100 # Each Frd_N refers to the Nth double precision register from Frd. 101 # Note that this adds twice N to the register number. 102 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 103 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 104 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 105 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 106 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 107 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 108 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 109 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 110 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 111 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 112 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 113 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 114 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 115 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 116 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 117 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 118 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 119 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 120 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 121 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 122 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 123 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 124 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 125 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 126 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 127 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 128 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 129 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 130 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 131 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 132 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 133 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 134 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 135 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 136 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 137 # Registers which are used explicitly in instructions 138 'R0': ('IntReg', 'udw', '0', None, 6), 139 'R1': ('IntReg', 'udw', '1', None, 7), 140 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 141 'R16': ('IntReg', 'udw', '16', None, 9), 142 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 143 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 144 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 145 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 146 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 147 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 148 149 # Control registers 150# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 151# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 152 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 153 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 154 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 155 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 156 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 157 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 158# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 159 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 160 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 161 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 162 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 163 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 164 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 165 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), 166 167 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 168 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 169 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 170 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 171 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 172 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 173 'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59), 174 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 175 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 176 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 177# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 178# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 179# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 180# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 181# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 182 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 183 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 184 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 185 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 186 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 187 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 188 189 'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69), 190 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 191 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 192 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 193 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 194 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 195 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 196 197 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), 198 # Mem gets a large number so it's always last 199 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 200 201}};