Cross Reference: /gem5/src/arch/sparc/isa/operands.isa

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operands.isa (3279:cf42adf4588f)	operands.isa (3381:0897959bf0e0)
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : ('signed int', 8), 33 'ub' : ('unsigned int', 8), 34 'shw' : ('signed int', 16), 35 'uhw' : ('unsigned int', 16), 36 'sw' : ('signed int', 32), 37 'uw' : ('unsigned int', 32), 38 'sdw' : ('signed int', 64), 39 'udw' : ('unsigned int', 64), 40 'sf' : ('float', 32), 41 'df' : ('float', 64), 42 'qf' : ('float', 128) 43}}; 44 45output header {{ 46 // A function to "decompress" double and quad floating point 47 // register numbers stuffed into 5 bit fields. These have their 48 // MSB put in the LSB position but are otherwise normal. 49 static inline unsigned int dfpr(unsigned int regNum) 50 {	1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31def operand_types {{ 32 'sb' : ('signed int', 8), 33 'ub' : ('unsigned int', 8), 34 'shw' : ('signed int', 16), 35 'uhw' : ('unsigned int', 16), 36 'sw' : ('signed int', 32), 37 'uw' : ('unsigned int', 32), 38 'sdw' : ('signed int', 64), 39 'udw' : ('unsigned int', 64), 40 'sf' : ('float', 32), 41 'df' : ('float', 64), 42 'qf' : ('float', 128) 43}}; 44 45output header {{ 46 // A function to "decompress" double and quad floating point 47 // register numbers stuffed into 5 bit fields. These have their 48 // MSB put in the LSB position but are otherwise normal. 49 static inline unsigned int dfpr(unsigned int regNum) 50 {
51 return regNum \| ((regNum & 1) << 5);	51 return (regNum & (~1)) \| ((regNum & 1) << 5);
52 } 53}}; 54 55def operands {{ 56 # Int regs default to unsigned, but code should not count on this. 57 # For clarity, descriptions that depend on unsigned behavior should 58 # explicitly specify '.uq'. 59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 61 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 3), 62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 64 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 65 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 66 # Each Frd_N refers to the Nth double precision register from Frd. 67 # Note that this adds twice N to the register number. 68 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 69 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 70 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 71 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 72 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 73 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 74 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 75 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 76 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 77 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 78 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 79 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 80 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 83 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 84 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 85 'R0': ('IntReg', 'udw', '0', None, 6), 86 'R1': ('IntReg', 'udw', '1', None, 7), 87 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 88 'R16': ('IntReg', 'udw', '16', None, 9), 89 90 # Control registers 91 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 92 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 93 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 94 95 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 96 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 97 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 98 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 99 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), 100 101 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 102 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 103 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 104 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 105 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 106 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 107 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 108 109 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 110 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56) 111 112}};	52 } 53}}; 54 55def operands {{ 56 # Int regs default to unsigned, but code should not count on this. 57 # For clarity, descriptions that depend on unsigned behavior should 58 # explicitly specify '.uq'. 59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), 60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 61 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 3), 62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 64 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 65 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 66 # Each Frd_N refers to the Nth double precision register from Frd. 67 # Note that this adds twice N to the register number. 68 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 69 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 70 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 71 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 72 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 73 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 74 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 75 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 76 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 77 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 78 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 79 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 80 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), 81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 83 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 84 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 85 'R0': ('IntReg', 'udw', '0', None, 6), 86 'R1': ('IntReg', 'udw', '1', None, 7), 87 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 88 'R16': ('IntReg', 'udw', '16', None, 9), 89 90 # Control registers 91 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 92 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 93 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 94 95 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 96 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 97 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 98 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 99 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), 100 101 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 102 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 103 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 104 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 105 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 106 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 107 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 108 109 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 110 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56) 111 112}};