1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'shw' : ('signed int', 16),
35 'uhw' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'sdw' : ('signed int', 64),
39 'udw' : ('unsigned int', 64),
40 'tudw' : ('twin64 int', 64),
41 'tuw' : ('twin32 int', 32),
42 'sf' : ('float', 32),
43 'df' : ('float', 64),
44 'qf' : ('float', 128)
45}};
46
47output header {{
48 // A function to "decompress" double and quad floating point
49 // register numbers stuffed into 5 bit fields. These have their
50 // MSB put in the LSB position but are otherwise normal.
51 static inline unsigned int dfpr(unsigned int regNum)
52 {
53 return (regNum & (~1)) | ((regNum & 1) << 5);
54 }
55}};
56
57def operands {{
58 # Int regs default to unsigned, but code should not count on this.
59 # For clarity, descriptions that depend on unsigned behavior should
60 # explicitly specify '.uq'.
61
62 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
63 # The Rd from the previous window
64 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
65 # The Rd from the next window
66 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
67 # For microcoded twin load instructions, RdTwin appears in the "code"
68 # for the instruction is replaced by RdLow or RdHigh by the format
69 # before it's processed by the iop.
70 # The low (even) register of a two register pair
71 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
72 # The high (odd) register of a two register pair
73 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
74 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
75 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
76 # A microcode register. Right now, this is the only one.
77 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
78 # Because double and quad precision register numbers are decoded
79 # differently, they get different operands. The single precision versions
80 # have an s post pended to their name.
81 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
82 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
83 # Each Frd_N refers to the Nth double precision register from Frd.
84 # Note that this adds twice N to the register number.
85 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
86 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
87 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
88 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
89 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
90 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
91 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
92 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
93 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
94 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
95 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
96 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
97 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
98 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
99 # Registers which are used explicitly in instructions
100 'R0': ('IntReg', 'udw', '0', None, 6),
101 'R1': ('IntReg', 'udw', '1', None, 7),
102 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
103 'R16': ('IntReg', 'udw', '16', None, 9),
104 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
105 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
106 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
107 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13),
108 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14),
109 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
110
111 # Control registers
112# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
113# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
114 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
115 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
116 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
117 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
118 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
119 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
120 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
121 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
122 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
123 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
124 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
125 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
126 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
127
128 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
129 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
130 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
131 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
132 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
133 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
134 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
135 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
136 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
137 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
138# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
139# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
140# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
141# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
142# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
143 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
144 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
145 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
146 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
147 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
148 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
149
150 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
151 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
152 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
153 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
154 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
155 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
156 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
157
158 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
159 # Mem gets a large number so it's always last
160 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
161
162}};