1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 38 unchanged lines hidden (view full) ---

47output header {{
48 // A function to "decompress" double and quad floating point
49 // register numbers stuffed into 5 bit fields. These have their
50 // MSB put in the LSB position but are otherwise normal.
51 static inline unsigned int dfpr(unsigned int regNum)
52 {
53 return (regNum & (~1)) | ((regNum & 1) << 5);
54 }
55}};
56
57def operands {{
58 # Int regs default to unsigned, but code should not count on this.
59 # For clarity, descriptions that depend on unsigned behavior should
60 # explicitly specify '.uq'.
61
62 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),

--- 11 unchanged lines hidden (view full) ---

74 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
75 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
76 # A microcode register. Right now, this is the only one.
77 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
78 # Because double and quad precision register numbers are decoded
79 # differently, they get different operands. The single precision versions
80 # have an s post pended to their name.
81 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
82 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
83 # Each Frd_N refers to the Nth double precision register from Frd.
84 # Note that this adds twice N to the register number.
85 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
86 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
87 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
88 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
89 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
90 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
91 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
92 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
93 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
94 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
95 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
96 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
97 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
98 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
99 # Registers which are used explicitly in instructions
100 'R0': ('IntReg', 'udw', '0', None, 6),
101 'R1': ('IntReg', 'udw', '1', None, 7),
102 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
103 'R16': ('IntReg', 'udw', '16', None, 9),
104 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),

--- 58 unchanged lines hidden ---