1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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51 return (regNum & (~1)) | ((regNum & 1) << 5);
52 }
53}};
54
55def operands {{
56 # Int regs default to unsigned, but code should not count on this.
57 # For clarity, descriptions that depend on unsigned behavior should
58 # explicitly specify '.uq'.
59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
61 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
64 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
65 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
66 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
67 # Each Frd_N refers to the Nth double precision register from Frd.
68 # Note that this adds twice N to the register number.
69 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
70 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
71 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
72 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
73 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
74 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
75 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
76 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
77 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
78 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
79 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
80 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
83 'R0': ('IntReg', 'udw', '0', None, 6),
84 'R1': ('IntReg', 'udw', '1', None, 7),
85 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
86 'R16': ('IntReg', 'udw', '16', None, 9),
87
88 # Control registers
89 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
90 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
91 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
92 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
93 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
94 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
95 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
96 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
97 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
98 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),

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104 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
105 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
106 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
107 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
108 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
109 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
110 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
111 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
112 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
113 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
114 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
115 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
116 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
117 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
118 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
119
120 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
121 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
122 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
123 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
124 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
125 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
126 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
127
128 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
129 # Mem gets a large number so it's always last
130 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
131
132}};