priv.isa (5094:10b8551e3e3f) | priv.isa (7741:340b6f01d69b) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 36 unchanged lines hidden (view full) --- 45 SparcStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 std::string generateDisassembly(Addr pc, 50 const SymbolTable *symtab) const; 51 }; 52 | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 36 unchanged lines hidden (view full) --- 45 SparcStaticInst(mnem, _machInst, __opClass) 46 { 47 } 48 49 std::string generateDisassembly(Addr pc, 50 const SymbolTable *symtab) const; 51 }; 52 |
53 //This class is for instructions that explicitly read control 54 //registers. It provides a special generateDisassembly function. | 53 // This class is for instructions that explicitly read control 54 // registers. It provides a special generateDisassembly function. |
55 class RdPriv : public Priv 56 { 57 protected: | 55 class RdPriv : public Priv 56 { 57 protected: |
58 //Constructor | 58 // Constructor |
59 RdPriv(const char *mnem, ExtMachInst _machInst, 60 OpClass __opClass, char const * _regName) : 61 Priv(mnem, _machInst, __opClass), regName(_regName) 62 { 63 } 64 65 std::string generateDisassembly(Addr pc, 66 const SymbolTable *symtab) const; 67 68 char const * regName; 69 }; 70 | 59 RdPriv(const char *mnem, ExtMachInst _machInst, 60 OpClass __opClass, char const * _regName) : 61 Priv(mnem, _machInst, __opClass), regName(_regName) 62 { 63 } 64 65 std::string generateDisassembly(Addr pc, 66 const SymbolTable *symtab) const; 67 68 char const * regName; 69 }; 70 |
71 //This class is for instructions that explicitly write control 72 //registers. It provides a special generateDisassembly function. | 71 // This class is for instructions that explicitly write control 72 // registers. It provides a special generateDisassembly function. |
73 class WrPriv : public Priv 74 { 75 protected: | 73 class WrPriv : public Priv 74 { 75 protected: |
76 //Constructor | 76 // Constructor |
77 WrPriv(const char *mnem, ExtMachInst _machInst, 78 OpClass __opClass, char const * _regName) : 79 Priv(mnem, _machInst, __opClass), regName(_regName) 80 { 81 } 82 83 std::string generateDisassembly(Addr pc, 84 const SymbolTable *symtab) const; --- 12 unchanged lines hidden (view full) --- 97 OpClass __opClass) : 98 Priv(mnem, _machInst, __opClass), imm(SIMM13) 99 { 100 } 101 102 int32_t imm; 103 }; 104 | 77 WrPriv(const char *mnem, ExtMachInst _machInst, 78 OpClass __opClass, char const * _regName) : 79 Priv(mnem, _machInst, __opClass), regName(_regName) 80 { 81 } 82 83 std::string generateDisassembly(Addr pc, 84 const SymbolTable *symtab) const; --- 12 unchanged lines hidden (view full) --- 97 OpClass __opClass) : 98 Priv(mnem, _machInst, __opClass), imm(SIMM13) 99 { 100 } 101 102 int32_t imm; 103 }; 104 |
105 //This class is for instructions that explicitly write control 106 //registers. It provides a special generateDisassembly function. | 105 // This class is for instructions that explicitly write control 106 // registers. It provides a special generateDisassembly function. |
107 class WrPrivImm : public PrivImm 108 { 109 protected: | 107 class WrPrivImm : public PrivImm 108 { 109 protected: |
110 //Constructor | 110 // Constructor |
111 WrPrivImm(const char *mnem, ExtMachInst _machInst, 112 OpClass __opClass, char const * _regName) : 113 PrivImm(mnem, _machInst, __opClass), regName(_regName) 114 { 115 } 116 117 std::string generateDisassembly(Addr pc, 118 const SymbolTable *symtab) const; 119 120 char const * regName; 121 }; 122}}; 123 124output decoder {{ | 111 WrPrivImm(const char *mnem, ExtMachInst _machInst, 112 OpClass __opClass, char const * _regName) : 113 PrivImm(mnem, _machInst, __opClass), regName(_regName) 114 { 115 } 116 117 std::string generateDisassembly(Addr pc, 118 const SymbolTable *symtab) const; 119 120 char const * regName; 121 }; 122}}; 123 124output decoder {{ |
125 std::string Priv::generateDisassembly(Addr pc, 126 const SymbolTable *symtab) const | 125 std::string 126 Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const |
127 { 128 std::stringstream response; 129 130 printMnemonic(response, mnemonic); 131 132 return response.str(); 133 } 134 | 127 { 128 std::stringstream response; 129 130 printMnemonic(response, mnemonic); 131 132 return response.str(); 133 } 134 |
135 std::string RdPriv::generateDisassembly(Addr pc, 136 const SymbolTable *symtab) const | 135 std::string 136 RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const |
137 { 138 std::stringstream response; 139 140 printMnemonic(response, mnemonic); 141 142 ccprintf(response, " %%%s, ", regName); 143 printDestReg(response, 0); 144 145 return response.str(); 146 } 147 | 137 { 138 std::stringstream response; 139 140 printMnemonic(response, mnemonic); 141 142 ccprintf(response, " %%%s, ", regName); 143 printDestReg(response, 0); 144 145 return response.str(); 146 } 147 |
148 std::string WrPriv::generateDisassembly(Addr pc, 149 const SymbolTable *symtab) const | 148 std::string 149 WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const |
150 { 151 std::stringstream response; 152 153 printMnemonic(response, mnemonic); 154 155 ccprintf(response, " "); | 150 { 151 std::stringstream response; 152 153 printMnemonic(response, mnemonic); 154 155 ccprintf(response, " "); |
156 //If the first reg is %g0, don't print it. 157 //This improves readability 158 if(_srcRegIdx[0] != 0) 159 { | 156 // If the first reg is %g0, don't print it. 157 // This improves readability 158 if (_srcRegIdx[0] != 0) { |
160 printSrcReg(response, 0); 161 ccprintf(response, ", "); 162 } 163 printSrcReg(response, 1); 164 ccprintf(response, ", %%%s", regName); 165 166 return response.str(); 167 } 168 169 std::string WrPrivImm::generateDisassembly(Addr pc, 170 const SymbolTable *symtab) const 171 { 172 std::stringstream response; 173 174 printMnemonic(response, mnemonic); 175 176 ccprintf(response, " "); | 159 printSrcReg(response, 0); 160 ccprintf(response, ", "); 161 } 162 printSrcReg(response, 1); 163 ccprintf(response, ", %%%s", regName); 164 165 return response.str(); 166 } 167 168 std::string WrPrivImm::generateDisassembly(Addr pc, 169 const SymbolTable *symtab) const 170 { 171 std::stringstream response; 172 173 printMnemonic(response, mnemonic); 174 175 ccprintf(response, " "); |
177 //If the first reg is %g0, don't print it. 178 //This improves readability 179 if(_srcRegIdx[0] != 0) 180 { | 176 // If the first reg is %g0, don't print it. 177 // This improves readability 178 if (_srcRegIdx[0] != 0) { |
181 printSrcReg(response, 0); 182 ccprintf(response, ", "); 183 } 184 ccprintf(response, "0x%x, %%%s", imm, regName); 185 186 return response.str(); 187 } 188}}; --- 9 unchanged lines hidden (view full) --- 198 199def template PrivExecute {{ 200 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 201 Trace::InstRecord *traceData) const 202 { 203 %(op_decl)s; 204 %(op_rd)s; 205 | 179 printSrcReg(response, 0); 180 ccprintf(response, ", "); 181 } 182 ccprintf(response, "0x%x, %%%s", imm, regName); 183 184 return response.str(); 185 } 186}}; --- 9 unchanged lines hidden (view full) --- 196 197def template PrivExecute {{ 198 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 199 Trace::InstRecord *traceData) const 200 { 201 %(op_decl)s; 202 %(op_rd)s; 203 |
206 //If the processor isn't in privileged mode, fault out right away 207 if(%(check)s) | 204 // If the processor isn't in privileged mode, fault out right away 205 if (%(check)s) |
208 return new PrivilegedAction; 209 | 206 return new PrivilegedAction; 207 |
210 if(%(tlCheck)s) | 208 if (%(tlCheck)s) |
211 return new IllegalInstruction; 212 213 Fault fault = NoFault; 214 %(code)s; 215 %(op_wb)s; 216 return fault; 217 } 218}}; --- 85 unchanged lines hidden --- | 209 return new IllegalInstruction; 210 211 Fault fault = NoFault; 212 %(code)s; 213 %(op_wb)s; 214 return fault; 215 } 216}}; --- 85 unchanged lines hidden --- |