priv.isa (3627:1c91588389c5) priv.isa (3792:dae368e56d0e)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 221 unchanged lines hidden (view full) ---

230 regBase = 'RdPriv'
231 break
232 for mnem in ["wrhpr", "wrpr", "wr"]:
233 if name.startswith(mnem):
234 regName = name[len(mnem):]
235 name = mnem
236 regBase = 'WrPriv'
237 break
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 221 unchanged lines hidden (view full) ---

230 regBase = 'RdPriv'
231 break
232 for mnem in ["wrhpr", "wrpr", "wr"]:
233 if name.startswith(mnem):
234 regName = name[len(mnem):]
235 name = mnem
236 regBase = 'WrPriv'
237 break
238 iop = InstObjParams(name, Name, regBase, code,
239 opt_flags, {"check": checkCode, "reg_name": regName})
238 iop = InstObjParams(name, Name, regBase,
239 {"code": code, "check": checkCode, "reg_name": regName},
240 opt_flags)
240 header_output = BasicDeclare.subst(iop)
241 if regName == '':
242 decoder_output = BasicConstructor.subst(iop)
243 else:
244 decoder_output = ControlRegConstructor.subst(iop)
245 exec_output = PrivExecute.subst(iop)
246 if usesImm:
247 imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm',
241 header_output = BasicDeclare.subst(iop)
242 if regName == '':
243 decoder_output = BasicConstructor.subst(iop)
244 else:
245 decoder_output = ControlRegConstructor.subst(iop)
246 exec_output = PrivExecute.subst(iop)
247 if usesImm:
248 imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm',
248 immCode, opt_flags, {"check": checkCode, "reg_name": regName})
249 {"code": immCode, "check": checkCode, "reg_name": regName},
250 opt_flags)
249 header_output += BasicDeclare.subst(imm_iop)
250 if regName == '':
251 decoder_output += BasicConstructor.subst(imm_iop)
252 else:
253 decoder_output += ControlRegConstructor.subst(imm_iop)
254 exec_output += PrivExecute.subst(imm_iop)
255 decode_block = ROrImmDecode.subst(iop)
256 else:

--- 35 unchanged lines hidden --- 		251 header_output += BasicDeclare.subst(imm_iop)
252 if regName == '':
253 decoder_output += BasicConstructor.subst(imm_iop)
254 else:
255 decoder_output += ControlRegConstructor.subst(imm_iop)
256 exec_output += PrivExecute.subst(imm_iop)
257 decode_block = ROrImmDecode.subst(iop)
258 else:

--- 35 unchanged lines hidden ---