priv.isa (3587:841cf134f321) priv.isa (3599:fd83707783c7)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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45 SparcStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
49 std::string generateDisassembly(Addr pc,
50 const SymbolTable *symtab) const;
51 };
52
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 36 unchanged lines hidden (view full) ---

45 SparcStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
49 std::string generateDisassembly(Addr pc,
50 const SymbolTable *symtab) const;
51 };
52
53 //This class is for instructions that explicitly read control
54 //registers. It provides a special generateDisassembly function.
55 class RdPriv : public Priv
56 {
57 protected:
58 //Constructor
59 RdPriv(const char *mnem, ExtMachInst _machInst,
60 OpClass __opClass, char const * _regName) :
61 Priv(mnem, _machInst, __opClass), regName(_regName)
62 {
63 }
64
65 std::string generateDisassembly(Addr pc,
66 const SymbolTable *symtab) const;
67
68 char const * regName;
69 };
70
71 //This class is for instructions that explicitly write control
72 //registers. It provides a special generateDisassembly function.
73 class WrPriv : public Priv
74 {
75 protected:
76 //Constructor
77 WrPriv(const char *mnem, ExtMachInst _machInst,
78 OpClass __opClass, char const * _regName) :
79 Priv(mnem, _machInst, __opClass), regName(_regName)
80 {
81 }
82
83 std::string generateDisassembly(Addr pc,
84 const SymbolTable *symtab) const;
85
86 char const * regName;
87 };
88
53 /**
54 * Base class for privelege mode operations with immediates.
55 */
56 class PrivImm : public Priv
57 {
58 protected:
59 // Constructor
60 PrivImm(const char *mnem, ExtMachInst _machInst,
61 OpClass __opClass) :
62 Priv(mnem, _machInst, __opClass), imm(SIMM13)
63 {
64 }
65
66 int32_t imm;
67 };
68
89 /**
90 * Base class for privelege mode operations with immediates.
91 */
92 class PrivImm : public Priv
93 {
94 protected:
95 // Constructor
96 PrivImm(const char *mnem, ExtMachInst _machInst,
97 OpClass __opClass) :
98 Priv(mnem, _machInst, __opClass), imm(SIMM13)
99 {
100 }
101
102 int32_t imm;
103 };
104
105 //This class is for instructions that explicitly write control
106 //registers. It provides a special generateDisassembly function.
107 class WrPrivImm : public PrivImm
108 {
109 protected:
110 //Constructor
111 WrPrivImm(const char *mnem, ExtMachInst _machInst,
112 OpClass __opClass, char const * _regName) :
113 PrivImm(mnem, _machInst, __opClass), regName(_regName)
114 {
115 }
116
117 std::string generateDisassembly(Addr pc,
118 const SymbolTable *symtab) const;
119
120 char const * regName;
121 };
69}};
70
71output decoder {{
72 std::string Priv::generateDisassembly(Addr pc,
73 const SymbolTable *symtab) const
74 {
75 std::stringstream response;
76
77 printMnemonic(response, mnemonic);
78
79 return response.str();
80 }
122}};
123
124output decoder {{
125 std::string Priv::generateDisassembly(Addr pc,
126 const SymbolTable *symtab) const
127 {
128 std::stringstream response;
129
130 printMnemonic(response, mnemonic);
131
132 return response.str();
133 }
134
135 std::string RdPriv::generateDisassembly(Addr pc,
136 const SymbolTable *symtab) const
137 {
138 std::stringstream response;
139
140 printMnemonic(response, mnemonic);
141
142 ccprintf(response, " %%%s, ", regName);
143 printDestReg(response, 0);
144
145 return response.str();
146 }
147
148 std::string WrPriv::generateDisassembly(Addr pc,
149 const SymbolTable *symtab) const
150 {
151 std::stringstream response;
152
153 printMnemonic(response, mnemonic);
154
155 ccprintf(response, " ");
156 printSrcReg(response, 0);
157 ccprintf(response, ", ");
158 printSrcReg(response, 1);
159 ccprintf(response, ", %%%s", regName);
160
161 return response.str();
162 }
163
164 std::string WrPrivImm::generateDisassembly(Addr pc,
165 const SymbolTable *symtab) const
166 {
167 std::stringstream response;
168
169 printMnemonic(response, mnemonic);
170
171 ccprintf(response, " ");
172 printSrcReg(response, 0);
173 ccprintf(response, ", 0x%x, %%%s", imm, regName);
174
175 return response.str();
176 }
81}};
82
177}};
178
179def template ControlRegConstructor {{
180 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
181 : %(base_class)s("%(mnemonic)s", machInst,
182 %(op_class)s, "%(reg_name)s")
183 {
184 %(constructor)s;
185 }
186}};
187
83def template PrivExecute {{
84 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
85 Trace::InstRecord *traceData) const
86 {
87 %(op_decl)s;
88 %(op_rd)s;
89
90 //If the processor isn't in privileged mode, fault out right away

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97 return fault;
98 }
99}};
100
101let {{
102 def doPrivFormat(code, checkCode, name, Name, opt_flags):
103 (usesImm, code, immCode,
104 rString, iString) = splitOutImm(code)
188def template PrivExecute {{
189 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
190 Trace::InstRecord *traceData) const
191 {
192 %(op_decl)s;
193 %(op_rd)s;
194
195 //If the processor isn't in privileged mode, fault out right away

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202 return fault;
203 }
204}};
205
206let {{
207 def doPrivFormat(code, checkCode, name, Name, opt_flags):
208 (usesImm, code, immCode,
209 rString, iString) = splitOutImm(code)
105 iop = InstObjParams(name, Name, 'Priv', code,
106 opt_flags, {"check": checkCode})
210 #If these are rd, rdpr, rdhpr, wr, wrpr, or wrhpr instructions,
211 #cut any other info out of the mnemonic. Also pick a different
212 #base class.
213 regBase = 'Priv'
214 regName = ''
215 for mnem in ["rdhpr", "rdpr", "rd"]:
216 if name.startswith(mnem):
217 regName = name[len(mnem):]
218 name = mnem
219 regBase = 'RdPriv'
220 break
221 for mnem in ["wrhpr", "wrpr", "wr"]:
222 if name.startswith(mnem):
223 regName = name[len(mnem):]
224 name = mnem
225 regBase = 'WrPriv'
226 break
227 iop = InstObjParams(name, Name, regBase, code,
228 opt_flags, {"check": checkCode, "reg_name": regName})
107 header_output = BasicDeclare.subst(iop)
229 header_output = BasicDeclare.subst(iop)
108 decoder_output = BasicConstructor.subst(iop)
230 if regName == '':
231 decoder_output = BasicConstructor.subst(iop)
232 else:
233 decoder_output = ControlRegConstructor.subst(iop)
109 exec_output = PrivExecute.subst(iop)
110 if usesImm:
234 exec_output = PrivExecute.subst(iop)
235 if usesImm:
111 imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
112 immCode, opt_flags, {"check": checkCode})
236 imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm',
237 immCode, opt_flags, {"check": checkCode, "reg_name": regName})
113 header_output += BasicDeclare.subst(imm_iop)
238 header_output += BasicDeclare.subst(imm_iop)
114 decoder_output += BasicConstructor.subst(imm_iop)
239 if regName == '':
240 decoder_output += BasicConstructor.subst(imm_iop)
241 else:
242 decoder_output += ControlRegConstructor.subst(imm_iop)
115 exec_output += PrivExecute.subst(imm_iop)
116 decode_block = ROrImmDecode.subst(iop)
117 else:
118 decode_block = BasicDecode.subst(iop)
119 return (header_output, decoder_output, exec_output, decode_block)
120}};
121
122def format Priv(code, *opt_flags) {{

--- 30 unchanged lines hidden --- 		243 exec_output += PrivExecute.subst(imm_iop)
244 decode_block = ROrImmDecode.subst(iop)
245 else:
246 decode_block = BasicDecode.subst(iop)
247 return (header_output, decoder_output, exec_output, decode_block)
248}};
249
250def format Priv(code, *opt_flags) {{

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