priv.isa (2940:2ef8a5541c9b) | priv.isa (2944:10dcffb2904f) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67 }; 68 69}}; 70 71output decoder {{ 72 std::string Priv::generateDisassembly(Addr pc, 73 const SymbolTable *symtab) const 74 { | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67 }; 68 69}}; 70 71output decoder {{ 72 std::string Priv::generateDisassembly(Addr pc, 73 const SymbolTable *symtab) const 74 { |
75 return "Privileged Instruction"; | 75 std::stringstream response; 76 77 printMnemonic(response, mnemonic); 78 79 return response.str(); |
76 } 77}}; 78 79def template PrivExecute {{ 80 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 81 Trace::InstRecord *traceData) const 82 { 83 %(op_decl)s; --- 50 unchanged lines hidden --- | 80 } 81}}; 82 83def template PrivExecute {{ 84 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 85 Trace::InstRecord *traceData) const 86 { 87 %(op_decl)s; --- 50 unchanged lines hidden --- |