1// Copyright (c) 2006-2007 The Regents of The University of Michigan |
2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the --- 192 unchanged lines hidden (view full) --- 202 { 203 %(op_decl)s; 204 %(op_rd)s; 205 206 //If the processor isn't in privileged mode, fault out right away 207 if(%(check)s) 208 return new PrivilegedAction; 209 |
210 if(%(tlCheck)s) 211 return new IllegalInstruction; 212 |
213 Fault fault = NoFault; 214 %(code)s; 215 %(op_wb)s; 216 return fault; 217 } 218}}; 219 220let {{ |
221 def doPrivFormat(code, checkCode, name, Name, tlCheck, opt_flags): |
222 (usesImm, code, immCode, 223 rString, iString) = splitOutImm(code) 224 #If these are rd, rdpr, rdhpr, wr, wrpr, or wrhpr instructions, 225 #cut any other info out of the mnemonic. Also pick a different 226 #base class. 227 regBase = 'Priv' 228 regName = '' 229 for mnem in ["rdhpr", "rdpr", "rd"]: --- 4 unchanged lines hidden (view full) --- 234 break 235 for mnem in ["wrhpr", "wrpr", "wr"]: 236 if name.startswith(mnem): 237 regName = name[len(mnem):] 238 name = mnem 239 regBase = 'WrPriv' 240 break 241 iop = InstObjParams(name, Name, regBase, |
242 {"code": code, "check": checkCode, 243 "tlCheck": tlCheck, "reg_name": regName}, |
244 opt_flags) 245 header_output = BasicDeclare.subst(iop) 246 if regName == '': 247 decoder_output = BasicConstructor.subst(iop) 248 else: 249 decoder_output = ControlRegConstructor.subst(iop) 250 exec_output = PrivExecute.subst(iop) 251 if usesImm: 252 imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm', |
253 {"code": immCode, "check": checkCode, 254 "tlCheck": tlCheck, "reg_name": regName}, |
255 opt_flags) 256 header_output += BasicDeclare.subst(imm_iop) 257 if regName == '': 258 decoder_output += BasicConstructor.subst(imm_iop) 259 else: 260 decoder_output += ControlRegConstructor.subst(imm_iop) 261 exec_output += PrivExecute.subst(imm_iop) 262 decode_block = ROrImmDecode.subst(iop) 263 else: 264 decode_block = BasicDecode.subst(iop) 265 return (header_output, decoder_output, exec_output, decode_block) 266}}; 267 |
268def format Priv(code, extraCond=true, checkTl=false, *opt_flags) {{ 269 checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCond 270 if checkTl != "false": 271 tlCheck = "Tl == 0" 272 else: 273 tlCheck = "false" |
274 (header_output, decoder_output, 275 exec_output, decode_block) = doPrivFormat(code, |
276 checkCode, name, Name, tlCheck, opt_flags) |
277}}; 278 |
279def format NoPriv(code, checkTl=false, *opt_flags) {{ |
280 #Instructions which use this format don't really check for 281 #any particular mode, but the disassembly is performed 282 #using the control registers actual name 283 checkCode = "false" |
284 if checkTl != "false": 285 tlCheck = "Tl == 0" 286 else: 287 tlCheck = "false" |
288 (header_output, decoder_output, 289 exec_output, decode_block) = doPrivFormat(code, |
290 checkCode, name, Name, tlCheck, opt_flags) |
291}}; 292 |
293def format HPriv(code, checkTl=false, *opt_flags) {{ |
294 checkCode = "!Hpstate<2:2>" |
295 if checkTl != "false": 296 tlCheck = "Tl == 0" 297 else: 298 tlCheck = "false" |
299 (header_output, decoder_output, 300 exec_output, decode_block) = doPrivFormat(code, |
301 checkCode, name, Name, tlCheck, opt_flags) |
302}}; 303 |