1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the

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202 {
203 %(op_decl)s;
204 %(op_rd)s;
205
206 //If the processor isn't in privileged mode, fault out right away
207 if(%(check)s)
208 return new PrivilegedAction;
209
210 Fault fault = NoFault;
211 %(code)s;
212 %(op_wb)s;
213 return fault;
214 }
215}};
216
217let {{
218 def doPrivFormat(code, checkCode, name, Name, opt_flags):
219 (usesImm, code, immCode,
220 rString, iString) = splitOutImm(code)
221 #If these are rd, rdpr, rdhpr, wr, wrpr, or wrhpr instructions,
222 #cut any other info out of the mnemonic. Also pick a different
223 #base class.
224 regBase = 'Priv'
225 regName = ''
226 for mnem in ["rdhpr", "rdpr", "rd"]:

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231 break
232 for mnem in ["wrhpr", "wrpr", "wr"]:
233 if name.startswith(mnem):
234 regName = name[len(mnem):]
235 name = mnem
236 regBase = 'WrPriv'
237 break
238 iop = InstObjParams(name, Name, regBase,
239 {"code": code, "check": checkCode, "reg_name": regName},
240 opt_flags)
241 header_output = BasicDeclare.subst(iop)
242 if regName == '':
243 decoder_output = BasicConstructor.subst(iop)
244 else:
245 decoder_output = ControlRegConstructor.subst(iop)
246 exec_output = PrivExecute.subst(iop)
247 if usesImm:
248 imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm',
249 {"code": immCode, "check": checkCode, "reg_name": regName},
250 opt_flags)
251 header_output += BasicDeclare.subst(imm_iop)
252 if regName == '':
253 decoder_output += BasicConstructor.subst(imm_iop)
254 else:
255 decoder_output += ControlRegConstructor.subst(imm_iop)
256 exec_output += PrivExecute.subst(imm_iop)
257 decode_block = ROrImmDecode.subst(iop)
258 else:
259 decode_block = BasicDecode.subst(iop)
260 return (header_output, decoder_output, exec_output, decode_block)
261}};
262
263def format Priv(code, *opt_flags) {{
264 checkCode = "!(Pstate<2:> || Hpstate<2:>)"
265 (header_output, decoder_output,
266 exec_output, decode_block) = doPrivFormat(code,
267 checkCode, name, Name, opt_flags)
268}};
269
270def format NoPriv(code, *opt_flags) {{
271 #Instructions which use this format don't really check for
272 #any particular mode, but the disassembly is performed
273 #using the control registers actual name
274 checkCode = "false"
275 (header_output, decoder_output,
276 exec_output, decode_block) = doPrivFormat(code,
277 checkCode, name, Name, opt_flags)
278}};
279
280def format PrivCheck(code, extraCheckCode, *opt_flags) {{
281 checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode
282 (header_output, decoder_output,
283 exec_output, decode_block) = doPrivFormat(code,
284 checkCode, name, Name, opt_flags)
285}};
286
287def format HPriv(code, *opt_flags) {{
288 checkCode = "!Hpstate<2:2>"
289 (header_output, decoder_output,
290 exec_output, decode_block) = doPrivFormat(code,
291 checkCode, name, Name, opt_flags)
292}};
293