util.isa (3970:d54945bab95d) util.isa (3980:9bcb2a2e9bb8)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(fp_enable_check)s;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
147 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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165}};
166
167def template LoadInitiateAcc {{
168 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
169 Trace::InstRecord * traceData) const
170 {
171 Fault fault = NoFault;
172 Addr EA;
145 %(op_decl)s;
146 %(op_rd)s;
147 %(ea_code)s;
148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
149 %(fault_check)s;
150 if(fault == NoFault)
151 {
152 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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166}};
167
168def template LoadInitiateAcc {{
169 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
170 Trace::InstRecord * traceData) const
171 {
172 Fault fault = NoFault;
173 Addr EA;
174 %(fp_enable_check)s;
173 %(op_decl)s;
174 %(op_rd)s;
175 %(ea_code)s;
176 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
177 %(fault_check)s;
178 if(fault == NoFault)
179 {
180 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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205 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
206 Trace::InstRecord *traceData) const
207 {
208 Fault fault = NoFault;
209 //This is to support the conditional store in cas instructions.
210 //It should be optomized out in all the others
211 bool storeCond = true;
212 Addr EA;
175 %(op_decl)s;
176 %(op_rd)s;
177 %(ea_code)s;
178 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
179 %(fault_check)s;
180 if(fault == NoFault)
181 {
182 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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207 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
208 Trace::InstRecord *traceData) const
209 {
210 Fault fault = NoFault;
211 //This is to support the conditional store in cas instructions.
212 //It should be optomized out in all the others
213 bool storeCond = true;
214 Addr EA;
215 %(fp_enable_check)s;
213 %(op_decl)s;
214 %(op_rd)s;
215 %(ea_code)s;
216 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
217 %(fault_check)s;
218 if(fault == NoFault)
219 {
220 %(code)s;

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236
237def template StoreInitiateAcc {{
238 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
239 Trace::InstRecord * traceData) const
240 {
241 Fault fault = NoFault;
242 bool storeCond = true;
243 Addr EA;
216 %(op_decl)s;
217 %(op_rd)s;
218 %(ea_code)s;
219 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
220 %(fault_check)s;
221 if(fault == NoFault)
222 {
223 %(code)s;

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239
240def template StoreInitiateAcc {{
241 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
242 Trace::InstRecord * traceData) const
243 {
244 Fault fault = NoFault;
245 bool storeCond = true;
246 Addr EA;
247 %(fp_enable_check)s;
244 %(op_decl)s;
245 %(op_rd)s;
246 %(ea_code)s;
247 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
248 %(fault_check)s;
249 if(fault == NoFault)
250 {
251 %(code)s;

--- 96 unchanged lines hidden --- 		248 %(op_decl)s;
249 %(op_rd)s;
250 %(ea_code)s;
251 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
252 %(fault_check)s;
253 if(fault == NoFault)
254 {
255 %(code)s;

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