util.isa (3863:adf3ddd4bcde) util.isa (3931:de791fa53d04)
1// Copyright (c) 2006 The Regents of The University of Michigan
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the

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136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the

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136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(fp_enable_check)s;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
147 DPRINTF(Sparc, "The address is 0x%x\n", EA);
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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164 }
165
166 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
167 Trace::InstRecord * traceData) const
168 {
169 Fault fault = NoFault;
170 Addr EA;
171 uint%(mem_acc_size)s_t Mem;
145 %(op_decl)s;
146 %(op_rd)s;
147 %(ea_code)s;
148 DPRINTF(Sparc, "The address is 0x%x\n", EA);
149 %(fault_check)s;
150 if(fault == NoFault)
151 {
152 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);

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165 }
166
167 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
168 Trace::InstRecord * traceData) const
169 {
170 Fault fault = NoFault;
171 Addr EA;
172 uint%(mem_acc_size)s_t Mem;
173 %(fp_enable_check)s;
172 %(ea_decl)s;
173 %(ea_rd)s;
174 %(ea_code)s;
175 %(fault_check)s;
176 if(fault == NoFault)
177 {
178 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
179 }

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201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
202 Trace::InstRecord *traceData) const
203 {
204 Fault fault = NoFault;
205 //This is to support the conditional store in cas instructions.
206 //It should be optomized out in all the others
207 bool storeCond = true;
208 Addr EA;
174 %(ea_decl)s;
175 %(ea_rd)s;
176 %(ea_code)s;
177 %(fault_check)s;
178 if(fault == NoFault)
179 {
180 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
181 }

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203 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
204 Trace::InstRecord *traceData) const
205 {
206 Fault fault = NoFault;
207 //This is to support the conditional store in cas instructions.
208 //It should be optomized out in all the others
209 bool storeCond = true;
210 Addr EA;
211 %(fp_enable_check)s;
209 %(op_decl)s;
210 %(op_rd)s;
211 %(ea_code)s;
212 DPRINTF(Sparc, "The address is 0x%x\n", EA);
213 %(fault_check)s;
214 if(fault == NoFault)
215 {
216 %(code)s;

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230 }
231
232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
233 Trace::InstRecord * traceData) const
234 {
235 Fault fault = NoFault;
236 bool storeCond = true;
237 Addr EA;
212 %(op_decl)s;
213 %(op_rd)s;
214 %(ea_code)s;
215 DPRINTF(Sparc, "The address is 0x%x\n", EA);
216 %(fault_check)s;
217 if(fault == NoFault)
218 {
219 %(code)s;

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233 }
234
235 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
236 Trace::InstRecord * traceData) const
237 {
238 Fault fault = NoFault;
239 bool storeCond = true;
240 Addr EA;
241 %(fp_enable_check)s;
238 %(op_decl)s;
239 %(op_rd)s;
240 %(ea_code)s;
241 DPRINTF(Sparc, "The address is 0x%x\n", EA);
242 %(fault_check)s;
243 if(fault == NoFault)
244 {
245 %(code)s;

--- 101 unchanged lines hidden --- 		242 %(op_decl)s;
243 %(op_rd)s;
244 %(ea_code)s;
245 DPRINTF(Sparc, "The address is 0x%x\n", EA);
246 %(fault_check)s;
247 if(fault == NoFault)
248 {
249 %(code)s;

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