util.isa (3810:c2caa5f3f09f) util.isa (3823:1c8f87aa103e)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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143 Addr EA;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
147 DPRINTF(Sparc, "The address is 0x%x\n", EA);
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 134 unchanged lines hidden (view full) ---

143 Addr EA;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
147 DPRINTF(Sparc, "The address is 0x%x\n", EA);
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
152 }
153 if(fault == NoFault)
154 {
155 %(code)s;
156 }
157 if(fault == NoFault)
158 {
159 //Write the resulting state to the execution context

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170 Addr EA;
171 uint%(mem_acc_size)s_t Mem;
172 %(ea_decl)s;
173 %(ea_rd)s;
174 %(ea_code)s;
175 %(fault_check)s;
176 if(fault == NoFault)
177 {
152 }
153 if(fault == NoFault)
154 {
155 %(code)s;
156 }
157 if(fault == NoFault)
158 {
159 //Write the resulting state to the execution context

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170 Addr EA;
171 uint%(mem_acc_size)s_t Mem;
172 %(ea_decl)s;
173 %(ea_rd)s;
174 %(ea_code)s;
175 %(fault_check)s;
176 if(fault == NoFault)
177 {
178 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
178 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
179 }
180 return fault;
181 }
182
183 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
184 Trace::InstRecord * traceData) const
185 {
186 Fault fault = NoFault;

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283 fault = new IllegalInstruction;
284 else if(EA & 0x3f)
285 fault = new MemAddressNotAligned;
286 '''
287 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
288 # are split into ones that are available in priv and hpriv, and
289 # those that are only available in hpriv
290 AlternateASIPrivFaultCheck = '''
179 }
180 return fault;
181 }
182
183 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
184 Trace::InstRecord * traceData) const
185 {
186 Fault fault = NoFault;

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283 fault = new IllegalInstruction;
284 else if(EA & 0x3f)
285 fault = new MemAddressNotAligned;
286 '''
287 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
288 # are split into ones that are available in priv and hpriv, and
289 # those that are only available in hpriv
290 AlternateASIPrivFaultCheck = '''
291 if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
292 fault = new PrivilegedAction;
291 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
292 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
293 fault = new PrivilegedAction;
293 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
294 fault = new PrivilegedAction;
295 '''
296
297}};
298
299//A simple function to generate the name of the macro op of a certain
300//instruction at a certain micropc

--- 39 unchanged lines hidden --- 		294 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
295 fault = new PrivilegedAction;
296 '''
297
298}};
299
300//A simple function to generate the name of the macro op of a certain
301//instruction at a certain micropc

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