util.isa (3627:1c91588389c5) util.isa (3766:c220c2bdd06c)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 130 unchanged lines hidden (view full) ---

139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(op_decl)s;
145 %(op_rd)s;
146 %(ea_code)s;
147 DPRINTF(Sparc, "The address is 0x%x\n", EA);
147 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
152 }
153 if(fault == NoFault)
154 {
155 %(code)s;

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167 Trace::InstRecord * traceData) const
168 {
169 Fault fault = NoFault;
170 Addr EA;
171 uint%(mem_acc_size)s_t Mem;
172 %(ea_decl)s;
173 %(ea_rd)s;
174 %(ea_code)s;
148 %(fault_check)s;
149 if(fault == NoFault)
150 {
151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
152 }
153 if(fault == NoFault)
154 {
155 %(code)s;

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167 Trace::InstRecord * traceData) const
168 {
169 Fault fault = NoFault;
170 Addr EA;
171 uint%(mem_acc_size)s_t Mem;
172 %(ea_decl)s;
173 %(ea_rd)s;
174 %(ea_code)s;
175 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
175 %(fault_check)s;
176 if(fault == NoFault)
177 {
178 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
179 }
180 return fault;
181 }
182

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197}};
198
199//This template provides the execute functions for a store
200def template StoreExecute {{
201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
202 Trace::InstRecord *traceData) const
203 {
204 Fault fault = NoFault;
176 %(fault_check)s;
177 if(fault == NoFault)
178 {
179 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
180 }
181 return fault;
182 }
183

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198}};
199
200//This template provides the execute functions for a store
201def template StoreExecute {{
202 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
203 Trace::InstRecord *traceData) const
204 {
205 Fault fault = NoFault;
205 uint64_t write_result = 0;
206 //This is to support the conditional store in cas instructions.
207 //It should be optomized out in all the others
208 bool storeCond = true;
209 Addr EA;
210 %(op_decl)s;
211 %(op_rd)s;
212 %(ea_code)s;
206 //This is to support the conditional store in cas instructions.
207 //It should be optomized out in all the others
208 bool storeCond = true;
209 Addr EA;
210 %(op_decl)s;
211 %(op_rd)s;
212 %(ea_code)s;
213 DPRINTF(Sparc, "The address is 0x%x\n", EA);
213 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
214 %(fault_check)s;
215 if(fault == NoFault)
216 {
217 %(code)s;
218 }
219 if(storeCond && fault == NoFault)
220 {
214 %(fault_check)s;
215 if(fault == NoFault)
216 {
217 %(code)s;
218 }
219 if(storeCond && fault == NoFault)
220 {
221 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
221 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, 0);
222 }
223 if(fault == NoFault)
224 {
225 //Write the resulting state to the execution context
226 %(op_wb)s;
227 }
228
229 return fault;
230 }
231
232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
233 Trace::InstRecord * traceData) const
234 {
235 Fault fault = NoFault;
222 }
223 if(fault == NoFault)
224 {
225 //Write the resulting state to the execution context
226 %(op_wb)s;
227 }
228
229 return fault;
230 }
231
232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
233 Trace::InstRecord * traceData) const
234 {
235 Fault fault = NoFault;
236 uint64_t write_result = 0;
237 bool storeCond = true;
238 Addr EA;
239 %(op_decl)s;
240 %(op_rd)s;
241 %(ea_code)s;
236 bool storeCond = true;
237 Addr EA;
238 %(op_decl)s;
239 %(op_rd)s;
240 %(ea_code)s;
242 DPRINTF(Sparc, "The address is 0x%x\n", EA);
241 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
243 %(fault_check)s;
244 if(fault == NoFault)
245 {
246 %(code)s;
247 }
248 if(storeCond && fault == NoFault)
249 {
242 %(fault_check)s;
243 if(fault == NoFault)
244 {
245 %(code)s;
246 }
247 if(storeCond && fault == NoFault)
248 {
250 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
249 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, 0);
251 }
252 if(fault == NoFault)
253 {
254 //Write the resulting state to the execution context
255 %(op_wb)s;
256 }
257 return fault;
258 }

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251 if(fault == NoFault)
252 {
253 //Write the resulting state to the execution context
254 %(op_wb)s;
255 }
256 return fault;
257 }

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