1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic);
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic);
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82 if(store) 83 {
| 82 if (store) {
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84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "[");
| 83 printReg(response, _srcRegIdx[0]); 84 ccprintf(response, ", "); 85 } 86 ccprintf(response, "[");
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88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 {
| 87 if (_srcRegIdx[!store ? 0 : 1] != 0) {
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90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]");
| 88 printSrcReg(response, !store ? 0 : 1); 89 ccprintf(response, " + "); 90 } 91 printSrcReg(response, !store ? 1 : 2); 92 ccprintf(response, "]");
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95 if(load) 96 {
| 93 if (load) {
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97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic);
| 94 ccprintf(response, ", "); 95 printReg(response, _destRegIdx[0]); 96 } 97 98 return response.str(); 99 } 100 101 std::string MemImm::generateDisassembly(Addr pc, 102 const SymbolTable *symtab) const 103 { 104 std::stringstream response; 105 bool load = flags[IsLoad]; 106 bool save = flags[IsStore]; 107 108 printMnemonic(response, mnemonic);
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112 if(save) 113 {
| 109 if (save) {
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114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "[");
| 110 printReg(response, _srcRegIdx[0]); 111 ccprintf(response, ", "); 112 } 113 ccprintf(response, "[");
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118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 {
| 114 if (_srcRegIdx[!save ? 0 : 1] != 0) {
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120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 }
| 115 printReg(response, _srcRegIdx[!save ? 0 : 1]); 116 ccprintf(response, " + "); 117 }
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123 if(imm >= 0)
| 118 if (imm >= 0)
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124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm);
| 119 ccprintf(response, "0x%x]", imm); 120 else 121 ccprintf(response, "-0x%x]", -imm);
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127 if(load) 128 {
| 122 if (load) {
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129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136
| 123 ccprintf(response, ", "); 124 printReg(response, _destRegIdx[0]); 125 } 126 127 return response.str(); 128 } 129}}; 130
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137//This template provides the execute functions for a load
| 131// This template provides the execute functions for a load
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138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(fp_enable_check)s; 145 %(op_decl)s; 146 %(op_rd)s; 147 %(ea_code)s; 148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 149 %(fault_check)s;
| 132def template LoadExecute {{ 133 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 134 Trace::InstRecord *traceData) const 135 { 136 Fault fault = NoFault; 137 Addr EA; 138 %(fp_enable_check)s; 139 %(op_decl)s; 140 %(op_rd)s; 141 %(ea_code)s; 142 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 143 %(fault_check)s;
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150 if(fault == NoFault) 151 {
| 144 if (fault == NoFault) {
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152 %(EA_trunc)s 153 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 154 }
| 145 %(EA_trunc)s 146 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 147 }
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155 if(fault == NoFault) 156 {
| 148 if (fault == NoFault) {
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157 %(code)s; 158 }
| 149 %(code)s; 150 }
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159 if(fault == NoFault) 160 { 161 //Write the resulting state to the execution context 162 %(op_wb)s;
| 151 if (fault == NoFault) { 152 // Write the resulting state to the execution context 153 %(op_wb)s;
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163 } 164 165 return fault; 166 } 167}}; 168 169def template LoadInitiateAcc {{ 170 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 171 Trace::InstRecord * traceData) const 172 { 173 Fault fault = NoFault; 174 Addr EA; 175 %(fp_enable_check)s; 176 %(op_decl)s; 177 %(op_rd)s; 178 %(ea_code)s; 179 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 180 %(fault_check)s;
| 154 } 155 156 return fault; 157 } 158}}; 159 160def template LoadInitiateAcc {{ 161 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 162 Trace::InstRecord * traceData) const 163 { 164 Fault fault = NoFault; 165 Addr EA; 166 %(fp_enable_check)s; 167 %(op_decl)s; 168 %(op_rd)s; 169 %(ea_code)s; 170 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 171 %(fault_check)s;
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181 if(fault == NoFault) 182 {
| 172 if (fault == NoFault) {
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183 %(EA_trunc)s 184 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 185 } 186 return fault; 187 } 188}}; 189 190def template LoadCompleteAcc {{ 191 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 192 Trace::InstRecord * traceData) const 193 { 194 Fault fault = NoFault; 195 %(op_decl)s; 196 %(op_rd)s; 197 Mem = pkt->get<typeof(Mem)>(); 198 %(code)s;
| 173 %(EA_trunc)s 174 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); 175 } 176 return fault; 177 } 178}}; 179 180def template LoadCompleteAcc {{ 181 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 182 Trace::InstRecord * traceData) const 183 { 184 Fault fault = NoFault; 185 %(op_decl)s; 186 %(op_rd)s; 187 Mem = pkt->get<typeof(Mem)>(); 188 %(code)s;
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199 if(fault == NoFault) 200 {
| 189 if (fault == NoFault) {
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201 %(op_wb)s; 202 } 203 return fault; 204 } 205}}; 206
| 190 %(op_wb)s; 191 } 192 return fault; 193 } 194}}; 195
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207//This template provides the execute functions for a store
| 196// This template provides the execute functions for a store
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208def template StoreExecute {{ 209 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 210 Trace::InstRecord *traceData) const 211 { 212 Fault fault = NoFault;
| 197def template StoreExecute {{ 198 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 199 Trace::InstRecord *traceData) const 200 { 201 Fault fault = NoFault;
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213 //This is to support the conditional store in cas instructions. 214 //It should be optomized out in all the others
| 202 // This is to support the conditional store in cas instructions. 203 // It should be optomized out in all the others
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215 bool storeCond = true; 216 Addr EA; 217 %(fp_enable_check)s; 218 %(op_decl)s; 219 %(op_rd)s; 220 %(ea_code)s; 221 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 222 %(fault_check)s;
| 204 bool storeCond = true; 205 Addr EA; 206 %(fp_enable_check)s; 207 %(op_decl)s; 208 %(op_rd)s; 209 %(ea_code)s; 210 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 211 %(fault_check)s;
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223 if(fault == NoFault) 224 {
| 212 if (fault == NoFault) {
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225 %(code)s; 226 }
| 213 %(code)s; 214 }
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227 if(storeCond && fault == NoFault) 228 {
| 215 if (storeCond && fault == NoFault) {
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229 %(EA_trunc)s 230 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 231 EA, %(asi_val)s, 0); 232 }
| 216 %(EA_trunc)s 217 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 218 EA, %(asi_val)s, 0); 219 }
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233 if(fault == NoFault) 234 { 235 //Write the resulting state to the execution context 236 %(op_wb)s;
| 220 if (fault == NoFault) { 221 // Write the resulting state to the execution context 222 %(op_wb)s;
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237 } 238 239 return fault; 240 } 241}}; 242 243def template StoreInitiateAcc {{ 244 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 245 Trace::InstRecord * traceData) const 246 { 247 Fault fault = NoFault; 248 bool storeCond = true; 249 Addr EA; 250 %(fp_enable_check)s; 251 %(op_decl)s; 252 253 %(op_rd)s; 254 %(ea_code)s; 255 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 256 %(fault_check)s;
| 223 } 224 225 return fault; 226 } 227}}; 228 229def template StoreInitiateAcc {{ 230 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 231 Trace::InstRecord * traceData) const 232 { 233 Fault fault = NoFault; 234 bool storeCond = true; 235 Addr EA; 236 %(fp_enable_check)s; 237 %(op_decl)s; 238 239 %(op_rd)s; 240 %(ea_code)s; 241 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 242 %(fault_check)s;
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257 if(fault == NoFault) 258 {
| 243 if (fault == NoFault) {
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259 %(code)s; 260 }
| 244 %(code)s; 245 }
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261 if(storeCond && fault == NoFault) 262 {
| 246 if (storeCond && fault == NoFault) {
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263 %(EA_trunc)s 264 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 265 EA, %(asi_val)s, 0); 266 } 267 return fault; 268 } 269}}; 270 271def template StoreCompleteAcc {{ 272 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 273 Trace::InstRecord * traceData) const 274 { 275 return NoFault; 276 } 277}}; 278
| 247 %(EA_trunc)s 248 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, 249 EA, %(asi_val)s, 0); 250 } 251 return fault; 252 } 253}}; 254 255def template StoreCompleteAcc {{ 256 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 257 Trace::InstRecord * traceData) const 258 { 259 return NoFault; 260 } 261}}; 262
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279//This delcares the initiateAcc function in memory operations
| 263// This delcares the initiateAcc function in memory operations
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280def template InitiateAccDeclare {{ 281 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 282}}; 283
| 264def template InitiateAccDeclare {{ 265 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 266}}; 267
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284//This declares the completeAcc function in memory operations
| 268// This declares the completeAcc function in memory operations
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285def template CompleteAccDeclare {{ 286 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 287}}; 288
| 269def template CompleteAccDeclare {{ 270 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 271}}; 272
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289//Here are some code snippets which check for various fault conditions
| 273// Here are some code snippets which check for various fault conditions
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290let {{ 291 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 292 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 293 294 # The LSB can be zero, since it's really the MSB in doubles and quads 295 # and we're dealing with doubles 296 BlockAlignmentFaultCheck = '''
| 274let {{ 275 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 276 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 277 278 # The LSB can be zero, since it's really the MSB in doubles and quads 279 # and we're dealing with doubles 280 BlockAlignmentFaultCheck = '''
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297 if(RD & 0xe)
| 281 if (RD & 0xe)
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298 fault = new IllegalInstruction;
| 282 fault = new IllegalInstruction;
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299 else if(EA & 0x3f)
| 283 else if (EA & 0x3f)
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300 fault = new MemAddressNotAligned; 301 ''' 302 TwinAlignmentFaultCheck = '''
| 284 fault = new MemAddressNotAligned; 285 ''' 286 TwinAlignmentFaultCheck = '''
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303 if(RD & 0x1)
| 287 if (RD & 0x1)
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304 fault = new IllegalInstruction;
| 288 fault = new IllegalInstruction;
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305 else if(EA & 0xf)
| 289 else if (EA & 0xf)
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306 fault = new MemAddressNotAligned; 307 ''' 308 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 309 # are split into ones that are available in priv and hpriv, and 310 # those that are only available in hpriv 311 AlternateASIPrivFaultCheck = ''' 312 if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
| 290 fault = new MemAddressNotAligned; 291 ''' 292 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 293 # are split into ones that are available in priv and hpriv, and 294 # those that are only available in hpriv 295 AlternateASIPrivFaultCheck = ''' 296 if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
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313 !AsiIsUnPriv((ASI)EXT_ASI)) || 314 (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
| 297 !asiIsUnPriv((ASI)EXT_ASI)) || 298 (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI)))
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315 fault = new PrivilegedAction;
| 299 fault = new PrivilegedAction;
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316 else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
| 300 else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
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317 fault = new PrivilegedAction; 318 ''' 319 320 TruncateEA = ''' 321#if !FULL_SYSTEM 322 EA = Pstate<3:> ? EA<31:0> : EA; 323#endif 324 ''' 325}}; 326
| 301 fault = new PrivilegedAction; 302 ''' 303 304 TruncateEA = ''' 305#if !FULL_SYSTEM 306 EA = Pstate<3:> ? EA<31:0> : EA; 307#endif 308 ''' 309}}; 310
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327//A simple function to generate the name of the macro op of a certain 328//instruction at a certain micropc
| 311// A simple function to generate the name of the macro op of a certain 312// instruction at a certain micropc
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329let {{ 330 def makeMicroName(name, microPc): 331 return name + "::" + name + "_" + str(microPc) 332}}; 333
| 313let {{ 314 def makeMicroName(name, microPc): 315 return name + "::" + name + "_" + str(microPc) 316}}; 317
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334//This function properly generates the execute functions for one of the 335//templates above. This is needed because in one case, ea computation, 336//fault checks and the actual code all occur in the same function, 337//and in the other they're distributed across two. Also note that for 338//execute functions, the name of the base class doesn't matter.
| 318// This function properly generates the execute functions for one of the 319// templates above. This is needed because in one case, ea computation, 320// fault checks and the actual code all occur in the same function, 321// and in the other they're distributed across two. Also note that for 322// execute functions, the name of the base class doesn't matter.
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339let {{ 340 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 341 microParam["asi_val"] = asi; 342 iop = InstObjParams(name, Name, '', microParam, opt_flags) 343 (execf, initf, compf) = execute 344 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 345 346 347 def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute, 348 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 349 executeCode = '' 350 for (eaCode, name, Name) in ( 351 (eaRegCode, nameReg, NameReg), 352 (eaImmCode, nameImm, NameImm)): 353 microParams = {"code": code, "postacc_code" : postacc_code, 354 "ea_code": eaCode, "fault_check": faultCode, 355 "EA_trunc" : TruncateEA} 356 executeCode += doSplitExecute(execute, name, Name, 357 asi, opt_flags, microParams) 358 return executeCode 359}};
| 323let {{ 324 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 325 microParam["asi_val"] = asi; 326 iop = InstObjParams(name, Name, '', microParam, opt_flags) 327 (execf, initf, compf) = execute 328 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 329 330 331 def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute, 332 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 333 executeCode = '' 334 for (eaCode, name, Name) in ( 335 (eaRegCode, nameReg, NameReg), 336 (eaImmCode, nameImm, NameImm)): 337 microParams = {"code": code, "postacc_code" : postacc_code, 338 "ea_code": eaCode, "fault_check": faultCode, 339 "EA_trunc" : TruncateEA} 340 executeCode += doSplitExecute(execute, name, Name, 341 asi, opt_flags, microParams) 342 return executeCode 343}};
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