1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Mem utility templates and functions
34//
35
36output header {{
37 /**
38 * Base class for memory operations.
39 */
40 class Mem : public SparcStaticInst
41 {
42 protected:
43
44 // Constructor
45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
46 SparcStaticInst(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc,
51 const SymbolTable *symtab) const;
52 };
53
54 /**
55 * Class for memory operations which use an immediate offset.
56 */
57 class MemImm : public Mem
58 {
59 protected:
60
61 // Constructor
62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
64 {}
65
66 std::string generateDisassembly(Addr pc,
67 const SymbolTable *symtab) const;
68
69 const int32_t imm;
70 };
71}};
72
73output decoder {{
74 std::string Mem::generateDisassembly(Addr pc,
75 const SymbolTable *symtab) const
76 {
77 std::stringstream response;
78 bool load = flags[IsLoad];
79 bool store = flags[IsStore];
80
81 printMnemonic(response, mnemonic);
82 if(store)
83 {
84 printReg(response, _srcRegIdx[0]);
85 ccprintf(response, ", ");
86 }
87 ccprintf(response, "[");
88 if(_srcRegIdx[!store ? 0 : 1] != 0)
89 {
90 printSrcReg(response, !store ? 0 : 1);
91 ccprintf(response, " + ");
92 }
93 printSrcReg(response, !store ? 1 : 2);
94 ccprintf(response, "]");
95 if(load)
96 {
97 ccprintf(response, ", ");
98 printReg(response, _destRegIdx[0]);
99 }
100
101 return response.str();
102 }
103
104 std::string MemImm::generateDisassembly(Addr pc,
105 const SymbolTable *symtab) const
106 {
107 std::stringstream response;
108 bool load = flags[IsLoad];
109 bool save = flags[IsStore];
110
111 printMnemonic(response, mnemonic);
112 if(save)
113 {
114 printReg(response, _srcRegIdx[0]);
115 ccprintf(response, ", ");
116 }
117 ccprintf(response, "[");
118 if(_srcRegIdx[!save ? 0 : 1] != 0)
119 {
120 printReg(response, _srcRegIdx[!save ? 0 : 1]);
121 ccprintf(response, " + ");
122 }
123 if(imm >= 0)
124 ccprintf(response, "0x%x]", imm);
125 else
126 ccprintf(response, "-0x%x]", -imm);
127 if(load)
128 {
129 ccprintf(response, ", ");
130 printReg(response, _destRegIdx[0]);
131 }
132
133 return response.str();
134 }
135}};
136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(fp_enable_check)s;
145 %(op_decl)s;
146 %(op_rd)s;
147 %(ea_code)s;
148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
149 %(fault_check)s;
150 if(fault == NoFault)
151 {
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Mem utility templates and functions
34//
35
36output header {{
37 /**
38 * Base class for memory operations.
39 */
40 class Mem : public SparcStaticInst
41 {
42 protected:
43
44 // Constructor
45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
46 SparcStaticInst(mnem, _machInst, __opClass)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc,
51 const SymbolTable *symtab) const;
52 };
53
54 /**
55 * Class for memory operations which use an immediate offset.
56 */
57 class MemImm : public Mem
58 {
59 protected:
60
61 // Constructor
62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
64 {}
65
66 std::string generateDisassembly(Addr pc,
67 const SymbolTable *symtab) const;
68
69 const int32_t imm;
70 };
71}};
72
73output decoder {{
74 std::string Mem::generateDisassembly(Addr pc,
75 const SymbolTable *symtab) const
76 {
77 std::stringstream response;
78 bool load = flags[IsLoad];
79 bool store = flags[IsStore];
80
81 printMnemonic(response, mnemonic);
82 if(store)
83 {
84 printReg(response, _srcRegIdx[0]);
85 ccprintf(response, ", ");
86 }
87 ccprintf(response, "[");
88 if(_srcRegIdx[!store ? 0 : 1] != 0)
89 {
90 printSrcReg(response, !store ? 0 : 1);
91 ccprintf(response, " + ");
92 }
93 printSrcReg(response, !store ? 1 : 2);
94 ccprintf(response, "]");
95 if(load)
96 {
97 ccprintf(response, ", ");
98 printReg(response, _destRegIdx[0]);
99 }
100
101 return response.str();
102 }
103
104 std::string MemImm::generateDisassembly(Addr pc,
105 const SymbolTable *symtab) const
106 {
107 std::stringstream response;
108 bool load = flags[IsLoad];
109 bool save = flags[IsStore];
110
111 printMnemonic(response, mnemonic);
112 if(save)
113 {
114 printReg(response, _srcRegIdx[0]);
115 ccprintf(response, ", ");
116 }
117 ccprintf(response, "[");
118 if(_srcRegIdx[!save ? 0 : 1] != 0)
119 {
120 printReg(response, _srcRegIdx[!save ? 0 : 1]);
121 ccprintf(response, " + ");
122 }
123 if(imm >= 0)
124 ccprintf(response, "0x%x]", imm);
125 else
126 ccprintf(response, "-0x%x]", -imm);
127 if(load)
128 {
129 ccprintf(response, ", ");
130 printReg(response, _destRegIdx[0]);
131 }
132
133 return response.str();
134 }
135}};
136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(fp_enable_check)s;
145 %(op_decl)s;
146 %(op_rd)s;
147 %(ea_code)s;
148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
149 %(fault_check)s;
150 if(fault == NoFault)
151 {
|
152 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
| 152 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
|
153 }
154 if(fault == NoFault)
155 {
156 %(code)s;
157 }
158 if(fault == NoFault)
159 {
160 //Write the resulting state to the execution context
161 %(op_wb)s;
162 }
163
164 return fault;
165 }
166}};
167
168def template LoadInitiateAcc {{
169 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
170 Trace::InstRecord * traceData) const
171 {
172 Fault fault = NoFault;
173 Addr EA;
174 %(fp_enable_check)s;
175 %(op_decl)s;
176 %(op_rd)s;
177 %(ea_code)s;
178 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
179 %(fault_check)s;
180 if(fault == NoFault)
181 {
| 153 }
154 if(fault == NoFault)
155 {
156 %(code)s;
157 }
158 if(fault == NoFault)
159 {
160 //Write the resulting state to the execution context
161 %(op_wb)s;
162 }
163
164 return fault;
165 }
166}};
167
168def template LoadInitiateAcc {{
169 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
170 Trace::InstRecord * traceData) const
171 {
172 Fault fault = NoFault;
173 Addr EA;
174 %(fp_enable_check)s;
175 %(op_decl)s;
176 %(op_rd)s;
177 %(ea_code)s;
178 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
179 %(fault_check)s;
180 if(fault == NoFault)
181 {
|
182 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
| 182 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
|
183 }
184 return fault;
185 }
186}};
187
188def template LoadCompleteAcc {{
189 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
190 Trace::InstRecord * traceData) const
191 {
192 Fault fault = NoFault;
193 %(op_decl)s;
194 %(op_rd)s;
195 Mem = pkt->get<typeof(Mem)>();
196 %(code)s;
197 if(fault == NoFault)
198 {
199 %(op_wb)s;
200 }
201 return fault;
202 }
203}};
204
205//This template provides the execute functions for a store
206def template StoreExecute {{
207 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
208 Trace::InstRecord *traceData) const
209 {
210 Fault fault = NoFault;
211 //This is to support the conditional store in cas instructions.
212 //It should be optomized out in all the others
213 bool storeCond = true;
214 Addr EA;
215 %(fp_enable_check)s;
216 %(op_decl)s;
217 %(op_rd)s;
218 %(ea_code)s;
219 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
220 %(fault_check)s;
221 if(fault == NoFault)
222 {
223 %(code)s;
224 }
225 if(storeCond && fault == NoFault)
226 {
227 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
228 EA, %(asi_val)s, 0);
229 }
230 if(fault == NoFault)
231 {
232 //Write the resulting state to the execution context
233 %(op_wb)s;
234 }
235
236 return fault;
237 }
238}};
239
240def template StoreInitiateAcc {{
241 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
242 Trace::InstRecord * traceData) const
243 {
244 Fault fault = NoFault;
245 bool storeCond = true;
246 Addr EA;
247 %(fp_enable_check)s;
248 %(op_decl)s;
| 183 }
184 return fault;
185 }
186}};
187
188def template LoadCompleteAcc {{
189 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
190 Trace::InstRecord * traceData) const
191 {
192 Fault fault = NoFault;
193 %(op_decl)s;
194 %(op_rd)s;
195 Mem = pkt->get<typeof(Mem)>();
196 %(code)s;
197 if(fault == NoFault)
198 {
199 %(op_wb)s;
200 }
201 return fault;
202 }
203}};
204
205//This template provides the execute functions for a store
206def template StoreExecute {{
207 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
208 Trace::InstRecord *traceData) const
209 {
210 Fault fault = NoFault;
211 //This is to support the conditional store in cas instructions.
212 //It should be optomized out in all the others
213 bool storeCond = true;
214 Addr EA;
215 %(fp_enable_check)s;
216 %(op_decl)s;
217 %(op_rd)s;
218 %(ea_code)s;
219 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
220 %(fault_check)s;
221 if(fault == NoFault)
222 {
223 %(code)s;
224 }
225 if(storeCond && fault == NoFault)
226 {
227 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
228 EA, %(asi_val)s, 0);
229 }
230 if(fault == NoFault)
231 {
232 //Write the resulting state to the execution context
233 %(op_wb)s;
234 }
235
236 return fault;
237 }
238}};
239
240def template StoreInitiateAcc {{
241 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
242 Trace::InstRecord * traceData) const
243 {
244 Fault fault = NoFault;
245 bool storeCond = true;
246 Addr EA;
247 %(fp_enable_check)s;
248 %(op_decl)s;
|
| 249
|
249 %(op_rd)s;
250 %(ea_code)s;
251 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
252 %(fault_check)s;
253 if(fault == NoFault)
254 {
255 %(code)s;
256 }
257 if(storeCond && fault == NoFault)
258 {
259 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
260 EA, %(asi_val)s, 0);
261 }
262 if(fault == NoFault)
263 {
264 //Write the resulting state to the execution context
265 %(op_wb)s;
266 }
267 return fault;
268 }
269}};
270
271def template StoreCompleteAcc {{
272 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
273 Trace::InstRecord * traceData) const
274 {
275 return NoFault;
276 }
277}};
278
279//This delcares the initiateAcc function in memory operations
280def template InitiateAccDeclare {{
281 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
282}};
283
284//This declares the completeAcc function in memory operations
285def template CompleteAccDeclare {{
286 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
287}};
288
289//Here are some code snippets which check for various fault conditions
290let {{
291 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]
292 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc]
| 250 %(op_rd)s;
251 %(ea_code)s;
252 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
253 %(fault_check)s;
254 if(fault == NoFault)
255 {
256 %(code)s;
257 }
258 if(storeCond && fault == NoFault)
259 {
260 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
261 EA, %(asi_val)s, 0);
262 }
263 if(fault == NoFault)
264 {
265 //Write the resulting state to the execution context
266 %(op_wb)s;
267 }
268 return fault;
269 }
270}};
271
272def template StoreCompleteAcc {{
273 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
274 Trace::InstRecord * traceData) const
275 {
276 return NoFault;
277 }
278}};
279
280//This delcares the initiateAcc function in memory operations
281def template InitiateAccDeclare {{
282 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
283}};
284
285//This declares the completeAcc function in memory operations
286def template CompleteAccDeclare {{
287 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
288}};
289
290//Here are some code snippets which check for various fault conditions
291let {{
292 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]
293 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc]
|
| 294
|
293 # The LSB can be zero, since it's really the MSB in doubles and quads
294 # and we're dealing with doubles
295 BlockAlignmentFaultCheck = '''
296 if(RD & 0xe)
297 fault = new IllegalInstruction;
298 else if(EA & 0x3f)
299 fault = new MemAddressNotAligned;
300 '''
301 TwinAlignmentFaultCheck = '''
302 if(RD & 0x1)
303 fault = new IllegalInstruction;
304 else if(EA & 0xf)
305 fault = new MemAddressNotAligned;
306 '''
307 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
308 # are split into ones that are available in priv and hpriv, and
309 # those that are only available in hpriv
310 AlternateASIPrivFaultCheck = '''
311 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
312 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
313 fault = new PrivilegedAction;
314 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
315 fault = new PrivilegedAction;
316 '''
317
318}};
319
320//A simple function to generate the name of the macro op of a certain
321//instruction at a certain micropc
322let {{
323 def makeMicroName(name, microPc):
324 return name + "::" + name + "_" + str(microPc)
325}};
326
327//This function properly generates the execute functions for one of the
328//templates above. This is needed because in one case, ea computation,
329//fault checks and the actual code all occur in the same function,
330//and in the other they're distributed across two. Also note that for
331//execute functions, the name of the base class doesn't matter.
332let {{
333 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
334 microParam["asi_val"] = asi;
335 iop = InstObjParams(name, Name, '', microParam, opt_flags)
336 (execf, initf, compf) = execute
337 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop)
338
339
| 295 # The LSB can be zero, since it's really the MSB in doubles and quads
296 # and we're dealing with doubles
297 BlockAlignmentFaultCheck = '''
298 if(RD & 0xe)
299 fault = new IllegalInstruction;
300 else if(EA & 0x3f)
301 fault = new MemAddressNotAligned;
302 '''
303 TwinAlignmentFaultCheck = '''
304 if(RD & 0x1)
305 fault = new IllegalInstruction;
306 else if(EA & 0xf)
307 fault = new MemAddressNotAligned;
308 '''
309 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
310 # are split into ones that are available in priv and hpriv, and
311 # those that are only available in hpriv
312 AlternateASIPrivFaultCheck = '''
313 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
314 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
315 fault = new PrivilegedAction;
316 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
317 fault = new PrivilegedAction;
318 '''
319
320}};
321
322//A simple function to generate the name of the macro op of a certain
323//instruction at a certain micropc
324let {{
325 def makeMicroName(name, microPc):
326 return name + "::" + name + "_" + str(microPc)
327}};
328
329//This function properly generates the execute functions for one of the
330//templates above. This is needed because in one case, ea computation,
331//fault checks and the actual code all occur in the same function,
332//and in the other they're distributed across two. Also note that for
333//execute functions, the name of the base class doesn't matter.
334let {{
335 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
336 microParam["asi_val"] = asi;
337 iop = InstObjParams(name, Name, '', microParam, opt_flags)
338 (execf, initf, compf) = execute
339 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop)
340
341
|
340 def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
| 342 def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute,
|
341 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags):
342 executeCode = ''
343 for (eaCode, name, Name) in (
344 (eaRegCode, nameReg, NameReg),
345 (eaImmCode, nameImm, NameImm)):
| 343 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags):
344 executeCode = ''
345 for (eaCode, name, Name) in (
346 (eaRegCode, nameReg, NameReg),
347 (eaImmCode, nameImm, NameImm)):
|
346 microParams = {"code": code, "ea_code": eaCode,
347 "fault_check": faultCode}
| 348 microParams = {"code": code, "postacc_code" : postacc_code,
349 "ea_code": eaCode, "fault_check": faultCode}
|
348 executeCode += doSplitExecute(execute, name, Name,
349 asi, opt_flags, microParams)
350 return executeCode
351}};
| 350 executeCode += doSplitExecute(execute, name, Name,
351 asi, opt_flags, microParams)
352 return executeCode
353}};
|