util.isa (3952:092d03b2ab95) | util.isa (3954:d689b611d9dc) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic); 82 if(store) 83 { 84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "["); 88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 { 90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]"); 95 if(load) 96 { 97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic); 112 if(save) 113 { 114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "["); 118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 { 120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 } 123 if(imm >= 0) 124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm); 127 if(load) 128 { 129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136 137//This template provides the execute functions for a load 138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(op_decl)s; 145 %(op_rd)s; 146 %(ea_code)s; 147 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 148 %(fault_check)s; 149 if(fault == NoFault) 150 { 151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 152 } 153 if(fault == NoFault) 154 { 155 %(code)s; 156 } 157 if(fault == NoFault) 158 { 159 //Write the resulting state to the execution context 160 %(op_wb)s; 161 } 162 163 return fault; 164 } 165}}; 166 167def template LoadInitiateAcc {{ 168 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 169 Trace::InstRecord * traceData) const 170 { 171 Fault fault = NoFault; 172 Addr EA; | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic); 82 if(store) 83 { 84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "["); 88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 { 90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]"); 95 if(load) 96 { 97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic); 112 if(save) 113 { 114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "["); 118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 { 120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 } 123 if(imm >= 0) 124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm); 127 if(load) 128 { 129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136 137//This template provides the execute functions for a load 138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(op_decl)s; 145 %(op_rd)s; 146 %(ea_code)s; 147 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 148 %(fault_check)s; 149 if(fault == NoFault) 150 { 151 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 152 } 153 if(fault == NoFault) 154 { 155 %(code)s; 156 } 157 if(fault == NoFault) 158 { 159 //Write the resulting state to the execution context 160 %(op_wb)s; 161 } 162 163 return fault; 164 } 165}}; 166 167def template LoadInitiateAcc {{ 168 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 169 Trace::InstRecord * traceData) const 170 { 171 Fault fault = NoFault; 172 Addr EA; |
173 uint%(mem_acc_size)s_t Mem; | |
174 %(op_decl)s; 175 %(op_rd)s; 176 %(ea_code)s; 177 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 178 %(fault_check)s; 179 if(fault == NoFault) 180 { 181 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 182 } 183 return fault; 184 } 185}}; 186 187def template LoadCompleteAcc {{ 188 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 189 Trace::InstRecord * traceData) const 190 { 191 Fault fault = NoFault; 192 %(op_decl)s; 193 %(op_rd)s; 194 Mem = pkt->get<typeof(Mem)>(); 195 %(code)s; 196 if(fault == NoFault) 197 { 198 %(op_wb)s; 199 } 200 return fault; 201 } 202}}; 203 204//This template provides the execute functions for a store 205def template StoreExecute {{ 206 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 207 Trace::InstRecord *traceData) const 208 { 209 Fault fault = NoFault; 210 //This is to support the conditional store in cas instructions. 211 //It should be optomized out in all the others 212 bool storeCond = true; 213 Addr EA; 214 %(op_decl)s; 215 %(op_rd)s; 216 %(ea_code)s; 217 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 218 %(fault_check)s; 219 if(fault == NoFault) 220 { 221 %(code)s; 222 } 223 if(storeCond && fault == NoFault) 224 { 225 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 226 EA, %(asi_val)s, 0); 227 } 228 if(fault == NoFault) 229 { 230 //Write the resulting state to the execution context 231 %(op_wb)s; 232 } 233 234 return fault; 235 } 236}}; 237 238def template StoreInitiateAcc {{ 239 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 240 Trace::InstRecord * traceData) const 241 { 242 Fault fault = NoFault; 243 bool storeCond = true; 244 Addr EA; 245 %(op_decl)s; 246 %(op_rd)s; 247 %(ea_code)s; 248 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 249 %(fault_check)s; 250 if(fault == NoFault) 251 { 252 %(code)s; 253 } 254 if(storeCond && fault == NoFault) 255 { 256 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 257 EA, %(asi_val)s, 0); 258 } 259 if(fault == NoFault) 260 { 261 //Write the resulting state to the execution context 262 %(op_wb)s; 263 } 264 return fault; 265 } 266}}; 267 268def template StoreCompleteAcc {{ 269 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 270 Trace::InstRecord * traceData) const 271 { 272 return NoFault; 273 } 274}}; 275 276//This delcares the initiateAcc function in memory operations 277def template InitiateAccDeclare {{ 278 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 279}}; 280 281//This declares the completeAcc function in memory operations 282def template CompleteAccDeclare {{ 283 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 284}}; 285 286//Here are some code snippets which check for various fault conditions 287let {{ 288 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 289 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 290 # The LSB can be zero, since it's really the MSB in doubles and quads 291 # and we're dealing with doubles 292 BlockAlignmentFaultCheck = ''' 293 if(RD & 0xe) 294 fault = new IllegalInstruction; 295 else if(EA & 0x3f) 296 fault = new MemAddressNotAligned; 297 ''' | 173 %(op_decl)s; 174 %(op_rd)s; 175 %(ea_code)s; 176 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 177 %(fault_check)s; 178 if(fault == NoFault) 179 { 180 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 181 } 182 return fault; 183 } 184}}; 185 186def template LoadCompleteAcc {{ 187 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 188 Trace::InstRecord * traceData) const 189 { 190 Fault fault = NoFault; 191 %(op_decl)s; 192 %(op_rd)s; 193 Mem = pkt->get<typeof(Mem)>(); 194 %(code)s; 195 if(fault == NoFault) 196 { 197 %(op_wb)s; 198 } 199 return fault; 200 } 201}}; 202 203//This template provides the execute functions for a store 204def template StoreExecute {{ 205 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 206 Trace::InstRecord *traceData) const 207 { 208 Fault fault = NoFault; 209 //This is to support the conditional store in cas instructions. 210 //It should be optomized out in all the others 211 bool storeCond = true; 212 Addr EA; 213 %(op_decl)s; 214 %(op_rd)s; 215 %(ea_code)s; 216 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 217 %(fault_check)s; 218 if(fault == NoFault) 219 { 220 %(code)s; 221 } 222 if(storeCond && fault == NoFault) 223 { 224 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 225 EA, %(asi_val)s, 0); 226 } 227 if(fault == NoFault) 228 { 229 //Write the resulting state to the execution context 230 %(op_wb)s; 231 } 232 233 return fault; 234 } 235}}; 236 237def template StoreInitiateAcc {{ 238 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 239 Trace::InstRecord * traceData) const 240 { 241 Fault fault = NoFault; 242 bool storeCond = true; 243 Addr EA; 244 %(op_decl)s; 245 %(op_rd)s; 246 %(ea_code)s; 247 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 248 %(fault_check)s; 249 if(fault == NoFault) 250 { 251 %(code)s; 252 } 253 if(storeCond && fault == NoFault) 254 { 255 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 256 EA, %(asi_val)s, 0); 257 } 258 if(fault == NoFault) 259 { 260 //Write the resulting state to the execution context 261 %(op_wb)s; 262 } 263 return fault; 264 } 265}}; 266 267def template StoreCompleteAcc {{ 268 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 269 Trace::InstRecord * traceData) const 270 { 271 return NoFault; 272 } 273}}; 274 275//This delcares the initiateAcc function in memory operations 276def template InitiateAccDeclare {{ 277 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 278}}; 279 280//This declares the completeAcc function in memory operations 281def template CompleteAccDeclare {{ 282 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 283}}; 284 285//Here are some code snippets which check for various fault conditions 286let {{ 287 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 288 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 289 # The LSB can be zero, since it's really the MSB in doubles and quads 290 # and we're dealing with doubles 291 BlockAlignmentFaultCheck = ''' 292 if(RD & 0xe) 293 fault = new IllegalInstruction; 294 else if(EA & 0x3f) 295 fault = new MemAddressNotAligned; 296 ''' |
298 TwinAlignmentFaultCheck = ''' 299 if(RD & 0xe) 300 fault = new IllegalInstruction; 301 else if(EA & 0x1f) 302 fault = new MemAddressNotAligned; 303 ''' | |
304 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 305 # are split into ones that are available in priv and hpriv, and 306 # those that are only available in hpriv 307 AlternateASIPrivFaultCheck = ''' 308 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || 309 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) 310 fault = new PrivilegedAction; 311 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 312 fault = new PrivilegedAction; 313 ''' 314 315}}; 316 317//A simple function to generate the name of the macro op of a certain 318//instruction at a certain micropc 319let {{ 320 def makeMicroName(name, microPc): 321 return name + "::" + name + "_" + str(microPc) 322}}; 323 324//This function properly generates the execute functions for one of the 325//templates above. This is needed because in one case, ea computation, 326//fault checks and the actual code all occur in the same function, 327//and in the other they're distributed across two. Also note that for 328//execute functions, the name of the base class doesn't matter. 329let {{ 330 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 331 microParam["asi_val"] = asi; 332 iop = InstObjParams(name, Name, '', microParam, opt_flags) 333 (execf, initf, compf) = execute 334 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 335 336 337 def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, 338 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 339 executeCode = '' 340 for (eaCode, name, Name) in ( 341 (eaRegCode, nameReg, NameReg), 342 (eaImmCode, nameImm, NameImm)): 343 microParams = {"code": code, "ea_code": eaCode, 344 "fault_check": faultCode} 345 executeCode += doSplitExecute(execute, name, Name, 346 asi, opt_flags, microParams) 347 return executeCode 348}}; | 297 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 298 # are split into ones that are available in priv and hpriv, and 299 # those that are only available in hpriv 300 AlternateASIPrivFaultCheck = ''' 301 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || 302 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) 303 fault = new PrivilegedAction; 304 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 305 fault = new PrivilegedAction; 306 ''' 307 308}}; 309 310//A simple function to generate the name of the macro op of a certain 311//instruction at a certain micropc 312let {{ 313 def makeMicroName(name, microPc): 314 return name + "::" + name + "_" + str(microPc) 315}}; 316 317//This function properly generates the execute functions for one of the 318//templates above. This is needed because in one case, ea computation, 319//fault checks and the actual code all occur in the same function, 320//and in the other they're distributed across two. Also note that for 321//execute functions, the name of the base class doesn't matter. 322let {{ 323 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 324 microParam["asi_val"] = asi; 325 iop = InstObjParams(name, Name, '', microParam, opt_flags) 326 (execf, initf, compf) = execute 327 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 328 329 330 def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, 331 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 332 executeCode = '' 333 for (eaCode, name, Name) in ( 334 (eaRegCode, nameReg, NameReg), 335 (eaImmCode, nameImm, NameImm)): 336 microParams = {"code": code, "ea_code": eaCode, 337 "fault_check": faultCode} 338 executeCode += doSplitExecute(execute, name, Name, 339 asi, opt_flags, microParams) 340 return executeCode 341}}; |