util.isa (3388:1c6ebfc4c20e) | util.isa (3391:3b6298cab636) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 37def template LoadExecute {{ 38 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 39 Trace::InstRecord *traceData) const 40 { 41 Fault fault = NoFault; 42 Addr EA; 43 %(op_decl)s; 44 %(op_rd)s; | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 37def template LoadExecute {{ 38 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 39 Trace::InstRecord *traceData) const 40 { 41 Fault fault = NoFault; 42 Addr EA; 43 %(op_decl)s; 44 %(op_rd)s; |
45 %(priv_check)s; | |
46 %(ea_code)s; 47 DPRINTF(Sparc, "The address is 0x%x\n", EA); | 45 %(ea_code)s; 46 DPRINTF(Sparc, "The address is 0x%x\n", EA); |
48 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); 49 %(code)s; | 47 %(fault_check)s; |
50 if(fault == NoFault) 51 { | 48 if(fault == NoFault) 49 { |
50 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); 51 } 52 if(fault == NoFault) 53 { 54 %(code)s; 55 } 56 if(fault == NoFault) 57 { |
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52 //Write the resulting state to the execution context 53 %(op_wb)s; 54 } 55 56 return fault; 57 } 58 59 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 60 Trace::InstRecord * traceData) const 61 { 62 Fault fault = NoFault; 63 Addr EA; 64 uint%(mem_acc_size)s_t Mem; 65 %(ea_decl)s; 66 %(ea_rd)s; | 58 //Write the resulting state to the execution context 59 %(op_wb)s; 60 } 61 62 return fault; 63 } 64 65 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 66 Trace::InstRecord * traceData) const 67 { 68 Fault fault = NoFault; 69 Addr EA; 70 uint%(mem_acc_size)s_t Mem; 71 %(ea_decl)s; 72 %(ea_rd)s; |
67 %(priv_check)s; | |
68 %(ea_code)s; | 73 %(ea_code)s; |
69 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); | 74 %(fault_check)s; 75 if(fault == NoFault) 76 { 77 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); 78 } |
70 return fault; 71 } 72 73 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 74 Trace::InstRecord * traceData) const 75 { 76 Fault fault = NoFault; 77 %(code_decl)s; --- 13 unchanged lines hidden (view full) --- 91 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 92 Trace::InstRecord *traceData) const 93 { 94 Fault fault = NoFault; 95 uint64_t write_result = 0; 96 Addr EA; 97 %(op_decl)s; 98 %(op_rd)s; | 79 return fault; 80 } 81 82 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 83 Trace::InstRecord * traceData) const 84 { 85 Fault fault = NoFault; 86 %(code_decl)s; --- 13 unchanged lines hidden (view full) --- 100 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 101 Trace::InstRecord *traceData) const 102 { 103 Fault fault = NoFault; 104 uint64_t write_result = 0; 105 Addr EA; 106 %(op_decl)s; 107 %(op_rd)s; |
99 %(priv_check)s; | |
100 %(ea_code)s; 101 DPRINTF(Sparc, "The address is 0x%x\n", EA); | 108 %(ea_code)s; 109 DPRINTF(Sparc, "The address is 0x%x\n", EA); |
102 %(code)s; 103 | 110 %(fault_check)s; |
104 if(fault == NoFault) 105 { | 111 if(fault == NoFault) 112 { |
113 %(code)s; 114 } 115 if(fault == NoFault) 116 { |
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106 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); 107 } 108 if(fault == NoFault) 109 { 110 //Write the resulting state to the execution context 111 %(op_wb)s; 112 } 113 114 return fault; 115 } 116 117 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 118 Trace::InstRecord * traceData) const 119 { 120 Fault fault = NoFault; 121 uint64_t write_result = 0; 122 Addr EA; 123 %(op_decl)s; 124 %(op_rd)s; | 117 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); 118 } 119 if(fault == NoFault) 120 { 121 //Write the resulting state to the execution context 122 %(op_wb)s; 123 } 124 125 return fault; 126 } 127 128 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 129 Trace::InstRecord * traceData) const 130 { 131 Fault fault = NoFault; 132 uint64_t write_result = 0; 133 Addr EA; 134 %(op_decl)s; 135 %(op_rd)s; |
125 %(priv_check)s; | |
126 %(ea_code)s; 127 DPRINTF(Sparc, "The address is 0x%x\n", EA); | 136 %(ea_code)s; 137 DPRINTF(Sparc, "The address is 0x%x\n", EA); |
128 %(code)s; | 138 %(fault_check)s; |
129 if(fault == NoFault) 130 { | 139 if(fault == NoFault) 140 { |
141 %(code)s; 142 } 143 if(fault == NoFault) 144 { |
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131 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); 132 } 133 if(fault == NoFault) 134 { 135 //Write the resulting state to the execution context 136 %(op_wb)s; 137 } 138 return fault; --- 11 unchanged lines hidden (view full) --- 150 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 151}}; 152 153//This declares the completeAcc function in memory operations 154def template CompleteAccDeclare {{ 155 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 156}}; 157 | 145 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); 146 } 147 if(fault == NoFault) 148 { 149 //Write the resulting state to the execution context 150 %(op_wb)s; 151 } 152 return fault; --- 11 unchanged lines hidden (view full) --- 164 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 165}}; 166 167//This declares the completeAcc function in memory operations 168def template CompleteAccDeclare {{ 169 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 170}}; 171 |
172//Here are some code snippets which check for various fault conditions 173let {{ 174 # The LSB can be zero, since it's really the MSB in doubles and quads 175 # and we're dealing with doubles 176 BlockAlignmentFaultCheck = ''' 177 if(RD & 0xe) 178 fault = new IllegalInstruction; 179 else if(EA & 0x3f) 180 fault = new MemAddressNotAligned; 181 ''' 182 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 183 # are split into ones that are available in priv and hpriv, and 184 # those that are only available in hpriv 185 AlternateASIPrivFaultCheck = ''' 186 if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0) 187 fault = new PrivilegedAction; 188 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 189 fault = new PrivilegedAction; 190 ''' 191 192}}; 193 194//A simple function to generate the name of the macro op of a certain 195//instruction at a certain micropc 196let {{ 197 def makeMicroName(name, microPc): 198 return name + "::" + name + "_" + str(microPc) 199}}; 200 |
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158//This function properly generates the execute functions for one of the 159//templates above. This is needed because in one case, ea computation, | 201//This function properly generates the execute functions for one of the 202//templates above. This is needed because in one case, ea computation, |
160//privelege checks and the actual code all occur in the same function, | 203//fault checks and the actual code all occur in the same function, |
161//and in the other they're distributed across two. Also note that for 162//execute functions, the name of the base class doesn't matter. 163let {{ 164 def doSplitExecute(code, eaRegCode, eaImmCode, execute, | 204//and in the other they're distributed across two. Also note that for 205//execute functions, the name of the base class doesn't matter. 206let {{ 207 def doSplitExecute(code, eaRegCode, eaImmCode, execute, |
165 priv, nameReg, nameImm, NameReg, NameImm, opt_flags): | 208 faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags): |
166 codeIop = InstObjParams(nameReg, NameReg, '', code, opt_flags) 167 executeCode = '' 168 for (eaCode, name, Name) in ( 169 (eaRegCode, nameReg, NameReg), 170 (eaImmCode, nameImm, NameImm)): 171 eaIop = InstObjParams(name, Name, '', eaCode, | 209 codeIop = InstObjParams(nameReg, NameReg, '', code, opt_flags) 210 executeCode = '' 211 for (eaCode, name, Name) in ( 212 (eaRegCode, nameReg, NameReg), 213 (eaImmCode, nameImm, NameImm)): 214 eaIop = InstObjParams(name, Name, '', eaCode, |
172 opt_flags, {"priv_check": priv}) | 215 opt_flags, {"fault_check": faultCode}) |
173 iop = InstObjParams(name, Name, '', code, opt_flags, | 216 iop = InstObjParams(name, Name, '', code, opt_flags, |
174 {"priv_check": priv, "ea_code" : eaCode}) | 217 {"fault_check": faultCode, "ea_code" : eaCode}) |
175 (iop.ea_decl, 176 iop.ea_rd, 177 iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) 178 (iop.code_decl, 179 iop.code_rd, 180 iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb) 181 executeCode += execute.subst(iop) 182 return executeCode 183}}; | 218 (iop.ea_decl, 219 iop.ea_rd, 220 iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) 221 (iop.code_decl, 222 iop.code_rd, 223 iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb) 224 executeCode += execute.subst(iop) 225 return executeCode 226}}; |