1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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74 std::string Mem::generateDisassembly(Addr pc,
75 const SymbolTable *symtab) const
76 {
77 std::stringstream response;
78 bool load = flags[IsLoad];
79 bool store = flags[IsStore];
80
81 printMnemonic(response, mnemonic);
82 if(store)
83 {
84 printReg(response, _srcRegIdx[0]);
85 ccprintf(response, ", ");
86 }
87 ccprintf(response, "[");
88 if(_srcRegIdx[!store ? 0 : 1] != 0)
89 {
90 printSrcReg(response, !store ? 0 : 1);
91 ccprintf(response, " + ");
92 }
93 printSrcReg(response, !store ? 1 : 2);
94 ccprintf(response, "]");
95 if(load)
96 {
97 ccprintf(response, ", ");
98 printReg(response, _destRegIdx[0]);
99 }
100
101 return response.str();
102 }
103
104 std::string MemImm::generateDisassembly(Addr pc,
105 const SymbolTable *symtab) const
106 {
107 std::stringstream response;
108 bool load = flags[IsLoad];
109 bool save = flags[IsStore];
110
111 printMnemonic(response, mnemonic);
112 if(save)
113 {
114 printReg(response, _srcRegIdx[0]);
115 ccprintf(response, ", ");
116 }
117 ccprintf(response, "[");
118 if(_srcRegIdx[!save ? 0 : 1] != 0)
119 {
120 printReg(response, _srcRegIdx[!save ? 0 : 1]);
121 ccprintf(response, " + ");
122 }
123 if(imm >= 0)
124 ccprintf(response, "0x%x]", imm);
125 else
126 ccprintf(response, "-0x%x]", -imm);
127 if(load)
128 {
129 ccprintf(response, ", ");
130 printReg(response, _destRegIdx[0]);
131 }
132
133 return response.str();
134 }
135}};
136
137//This template provides the execute functions for a load
138def template LoadExecute {{
139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143 Addr EA;
144 %(fp_enable_check)s;
145 %(op_decl)s;
146 %(op_rd)s;
147 %(ea_code)s;
148 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
149 %(fault_check)s;
150 if(fault == NoFault)
151 {
152 %(EA_trunc)s
153 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
154 }
155 if(fault == NoFault)
156 {
157 %(code)s;
158 }
159 if(fault == NoFault)
160 {
161 //Write the resulting state to the execution context
162 %(op_wb)s;
163 }
164
165 return fault;
166 }
167}};
168
169def template LoadInitiateAcc {{
170 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
171 Trace::InstRecord * traceData) const
172 {
173 Fault fault = NoFault;
174 Addr EA;
175 %(fp_enable_check)s;
176 %(op_decl)s;
177 %(op_rd)s;
178 %(ea_code)s;
179 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
180 %(fault_check)s;
181 if(fault == NoFault)
182 {
183 %(EA_trunc)s
184 fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
185 }
186 return fault;
187 }
188}};
189
190def template LoadCompleteAcc {{
191 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
192 Trace::InstRecord * traceData) const
193 {
194 Fault fault = NoFault;
195 %(op_decl)s;
196 %(op_rd)s;
197 Mem = pkt->get<typeof(Mem)>();
198 %(code)s;
199 if(fault == NoFault)
200 {
201 %(op_wb)s;
202 }
203 return fault;
204 }
205}};
206
207//This template provides the execute functions for a store
208def template StoreExecute {{
209 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
210 Trace::InstRecord *traceData) const
211 {
212 Fault fault = NoFault;
213 //This is to support the conditional store in cas instructions.
214 //It should be optomized out in all the others
215 bool storeCond = true;
216 Addr EA;
217 %(fp_enable_check)s;
218 %(op_decl)s;
219 %(op_rd)s;
220 %(ea_code)s;
221 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
222 %(fault_check)s;
223 if(fault == NoFault)
224 {
225 %(code)s;
226 }
227 if(storeCond && fault == NoFault)
228 {
229 %(EA_trunc)s
230 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
231 EA, %(asi_val)s, 0);
232 }
233 if(fault == NoFault)
234 {
235 //Write the resulting state to the execution context
236 %(op_wb)s;
237 }
238
239 return fault;
240 }
241}};
242
243def template StoreInitiateAcc {{
244 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,

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249 Addr EA;
250 %(fp_enable_check)s;
251 %(op_decl)s;
252
253 %(op_rd)s;
254 %(ea_code)s;
255 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
256 %(fault_check)s;
257 if(fault == NoFault)
258 {
259 %(code)s;
260 }
261 if(storeCond && fault == NoFault)
262 {
263 %(EA_trunc)s
264 fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
265 EA, %(asi_val)s, 0);
266 }
267 return fault;
268 }
269}};
270
271def template StoreCompleteAcc {{
272 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
273 Trace::InstRecord * traceData) const
274 {
275 return NoFault;
276 }
277}};
278
279//This delcares the initiateAcc function in memory operations
280def template InitiateAccDeclare {{
281 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
282}};
283
284//This declares the completeAcc function in memory operations
285def template CompleteAccDeclare {{
286 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
287}};
288
289//Here are some code snippets which check for various fault conditions
290let {{
291 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]
292 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc]
293
294 # The LSB can be zero, since it's really the MSB in doubles and quads
295 # and we're dealing with doubles
296 BlockAlignmentFaultCheck = '''
297 if(RD & 0xe)
298 fault = new IllegalInstruction;
299 else if(EA & 0x3f)
300 fault = new MemAddressNotAligned;
301 '''
302 TwinAlignmentFaultCheck = '''
303 if(RD & 0x1)
304 fault = new IllegalInstruction;
305 else if(EA & 0xf)
306 fault = new MemAddressNotAligned;
307 '''
308 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
309 # are split into ones that are available in priv and hpriv, and
310 # those that are only available in hpriv
311 AlternateASIPrivFaultCheck = '''
312 if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
313 !AsiIsUnPriv((ASI)EXT_ASI)) ||
314 (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
315 fault = new PrivilegedAction;
316 else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
317 fault = new PrivilegedAction;
318 '''
319
320 TruncateEA = '''
321#if !FULL_SYSTEM
322 EA = Pstate<3:> ? EA<31:0> : EA;
323#endif
324 '''
325}};
326
327//A simple function to generate the name of the macro op of a certain
328//instruction at a certain micropc
329let {{
330 def makeMicroName(name, microPc):
331 return name + "::" + name + "_" + str(microPc)
332}};
333
334//This function properly generates the execute functions for one of the
335//templates above. This is needed because in one case, ea computation,
336//fault checks and the actual code all occur in the same function,
337//and in the other they're distributed across two. Also note that for
338//execute functions, the name of the base class doesn't matter.
339let {{
340 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
341 microParam["asi_val"] = asi;
342 iop = InstObjParams(name, Name, '', microParam, opt_flags)
343 (execf, initf, compf) = execute
344 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop)
345
346

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