1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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37def template LoadExecute {{
38 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
39 Trace::InstRecord *traceData) const
40 {
41 Fault fault = NoFault;
42 Addr EA;
43 %(op_decl)s;
44 %(op_rd)s;
45 %(priv_check)s;
46 %(ea_code)s;
47 DPRINTF(Sparc, "The address is 0x%x\n", EA);
48 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
49 %(code)s;
50 if(fault == NoFault)
51 {
52 //Write the resulting state to the execution context
53 %(op_wb)s;
54 }
55
56 return fault;
57 }
58
59 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
60 Trace::InstRecord * traceData) const
61 {
62 Fault fault = NoFault;
63 Addr EA;
64 uint%(mem_acc_size)s_t Mem;
65 %(ea_decl)s;
66 %(ea_rd)s;
67 %(priv_check)s;
68 %(ea_code)s;
69 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
70 return fault;
71 }
72
73 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
74 Trace::InstRecord * traceData) const
75 {
76 Fault fault = NoFault;
77 %(code_decl)s;

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91 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
92 Trace::InstRecord *traceData) const
93 {
94 Fault fault = NoFault;
95 uint64_t write_result = 0;
96 Addr EA;
97 %(op_decl)s;
98 %(op_rd)s;
99 %(priv_check)s;
100 %(ea_code)s;
101 DPRINTF(Sparc, "The address is 0x%x\n", EA);
102 %(code)s;
103
104 if(fault == NoFault)
105 {
106 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
107 }
108 if(fault == NoFault)
109 {
110 //Write the resulting state to the execution context
111 %(op_wb)s;
112 }
113
114 return fault;
115 }
116
117 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
118 Trace::InstRecord * traceData) const
119 {
120 Fault fault = NoFault;
121 uint64_t write_result = 0;
122 Addr EA;
123 %(op_decl)s;
124 %(op_rd)s;
125 %(priv_check)s;
126 %(ea_code)s;
127 DPRINTF(Sparc, "The address is 0x%x\n", EA);
128 %(code)s;
129 if(fault == NoFault)
130 {
131 fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
132 }
133 if(fault == NoFault)
134 {
135 //Write the resulting state to the execution context
136 %(op_wb)s;
137 }
138 return fault;

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150 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
151}};
152
153//This declares the completeAcc function in memory operations
154def template CompleteAccDeclare {{
155 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
156}};
157
158//This function properly generates the execute functions for one of the
159//templates above. This is needed because in one case, ea computation,
160//privelege checks and the actual code all occur in the same function,
161//and in the other they're distributed across two. Also note that for
162//execute functions, the name of the base class doesn't matter.
163let {{
164 def doSplitExecute(code, eaRegCode, eaImmCode, execute,
165 priv, nameReg, nameImm, NameReg, NameImm, opt_flags):
166 codeIop = InstObjParams(nameReg, NameReg, '', code, opt_flags)
167 executeCode = ''
168 for (eaCode, name, Name) in (
169 (eaRegCode, nameReg, NameReg),
170 (eaImmCode, nameImm, NameImm)):
171 eaIop = InstObjParams(name, Name, '', eaCode,
172 opt_flags, {"priv_check": priv})
173 iop = InstObjParams(name, Name, '', code, opt_flags,
174 {"priv_check": priv, "ea_code" : eaCode})
175 (iop.ea_decl,
176 iop.ea_rd,
177 iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
178 (iop.code_decl,
179 iop.code_rd,
180 iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
181 executeCode += execute.subst(iop)
182 return executeCode
183}};