blockmem.isa (5096:eb06635e06ac) | blockmem.isa (7741:340b6f01d69b) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 86 unchanged lines hidden (view full) --- 95 std::string BlockMemMicro::generateDisassembly(Addr pc, 96 const SymbolTable *symtab) const 97 { 98 std::stringstream response; 99 bool load = flags[IsLoad]; 100 bool save = flags[IsStore]; 101 102 printMnemonic(response, mnemonic); | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 86 unchanged lines hidden (view full) --- 95 std::string BlockMemMicro::generateDisassembly(Addr pc, 96 const SymbolTable *symtab) const 97 { 98 std::stringstream response; 99 bool load = flags[IsLoad]; 100 bool save = flags[IsStore]; 101 102 printMnemonic(response, mnemonic); |
103 if(save) 104 { | 103 if (save) { |
105 printReg(response, _srcRegIdx[0]); 106 ccprintf(response, ", "); 107 } 108 ccprintf(response, "[ "); 109 printReg(response, _srcRegIdx[!save ? 0 : 1]); 110 ccprintf(response, " + "); 111 printReg(response, _srcRegIdx[!save ? 1 : 2]); 112 ccprintf(response, " ]"); | 104 printReg(response, _srcRegIdx[0]); 105 ccprintf(response, ", "); 106 } 107 ccprintf(response, "[ "); 108 printReg(response, _srcRegIdx[!save ? 0 : 1]); 109 ccprintf(response, " + "); 110 printReg(response, _srcRegIdx[!save ? 1 : 2]); 111 ccprintf(response, " ]"); |
113 if(load) 114 { | 112 if (load) { |
115 ccprintf(response, ", "); 116 printReg(response, _destRegIdx[0]); 117 } 118 119 return response.str(); 120 } 121 122 std::string BlockMemImmMicro::generateDisassembly(Addr pc, 123 const SymbolTable *symtab) const 124 { 125 std::stringstream response; 126 bool load = flags[IsLoad]; 127 bool save = flags[IsStore]; 128 129 printMnemonic(response, mnemonic); | 113 ccprintf(response, ", "); 114 printReg(response, _destRegIdx[0]); 115 } 116 117 return response.str(); 118 } 119 120 std::string BlockMemImmMicro::generateDisassembly(Addr pc, 121 const SymbolTable *symtab) const 122 { 123 std::stringstream response; 124 bool load = flags[IsLoad]; 125 bool save = flags[IsStore]; 126 127 printMnemonic(response, mnemonic); |
130 if(save) 131 { | 128 if (save) { |
132 printReg(response, _srcRegIdx[1]); 133 ccprintf(response, ", "); 134 } 135 ccprintf(response, "[ "); 136 printReg(response, _srcRegIdx[0]); | 129 printReg(response, _srcRegIdx[1]); 130 ccprintf(response, ", "); 131 } 132 ccprintf(response, "[ "); 133 printReg(response, _srcRegIdx[0]); |
137 if(imm >= 0) | 134 if (imm >= 0) |
138 ccprintf(response, " + 0x%x ]", imm); 139 else 140 ccprintf(response, " + -0x%x ]", -imm); | 135 ccprintf(response, " + 0x%x ]", imm); 136 else 137 ccprintf(response, " + -0x%x ]", -imm); |
141 if(load) 142 { | 138 if (load) { |
143 ccprintf(response, ", "); 144 printReg(response, _destRegIdx[0]); 145 } 146 147 return response.str(); 148 } 149 150}}; 151 152def template BlockMemDeclare {{ 153 /** 154 * Static instruction class for a block memory operation 155 */ 156 class %(class_name)s : public %(base_class)s 157 { 158 public: | 139 ccprintf(response, ", "); 140 printReg(response, _destRegIdx[0]); 141 } 142 143 return response.str(); 144 } 145 146}}; 147 148def template BlockMemDeclare {{ 149 /** 150 * Static instruction class for a block memory operation 151 */ 152 class %(class_name)s : public %(base_class)s 153 { 154 public: |
159 //Constructor | 155 // Constructor |
160 %(class_name)s(ExtMachInst machInst); 161 162 protected: 163 class %(class_name)s_0 : public %(base_class)sMicro 164 { 165 public: | 156 %(class_name)s(ExtMachInst machInst); 157 158 protected: 159 class %(class_name)s_0 : public %(base_class)sMicro 160 { 161 public: |
166 //Constructor | 162 // Constructor |
167 %(class_name)s_0(ExtMachInst machInst); 168 %(BasicExecDeclare)s 169 %(InitiateAccDeclare)s 170 %(CompleteAccDeclare)s 171 }; 172 173 class %(class_name)s_1 : public %(base_class)sMicro 174 { 175 public: | 163 %(class_name)s_0(ExtMachInst machInst); 164 %(BasicExecDeclare)s 165 %(InitiateAccDeclare)s 166 %(CompleteAccDeclare)s 167 }; 168 169 class %(class_name)s_1 : public %(base_class)sMicro 170 { 171 public: |
176 //Constructor | 172 // Constructor |
177 %(class_name)s_1(ExtMachInst machInst); 178 %(BasicExecDeclare)s 179 %(InitiateAccDeclare)s 180 %(CompleteAccDeclare)s 181 }; 182 183 class %(class_name)s_2 : public %(base_class)sMicro 184 { 185 public: | 173 %(class_name)s_1(ExtMachInst machInst); 174 %(BasicExecDeclare)s 175 %(InitiateAccDeclare)s 176 %(CompleteAccDeclare)s 177 }; 178 179 class %(class_name)s_2 : public %(base_class)sMicro 180 { 181 public: |
186 //Constructor | 182 // Constructor |
187 %(class_name)s_2(ExtMachInst machInst); 188 %(BasicExecDeclare)s 189 %(InitiateAccDeclare)s 190 %(CompleteAccDeclare)s 191 }; 192 193 class %(class_name)s_3 : public %(base_class)sMicro 194 { 195 public: | 183 %(class_name)s_2(ExtMachInst machInst); 184 %(BasicExecDeclare)s 185 %(InitiateAccDeclare)s 186 %(CompleteAccDeclare)s 187 }; 188 189 class %(class_name)s_3 : public %(base_class)sMicro 190 { 191 public: |
196 //Constructor | 192 // Constructor |
197 %(class_name)s_3(ExtMachInst machInst); 198 %(BasicExecDeclare)s 199 %(InitiateAccDeclare)s 200 %(CompleteAccDeclare)s 201 }; 202 203 class %(class_name)s_4 : public %(base_class)sMicro 204 { 205 public: | 193 %(class_name)s_3(ExtMachInst machInst); 194 %(BasicExecDeclare)s 195 %(InitiateAccDeclare)s 196 %(CompleteAccDeclare)s 197 }; 198 199 class %(class_name)s_4 : public %(base_class)sMicro 200 { 201 public: |
206 //Constructor | 202 // Constructor |
207 %(class_name)s_4(ExtMachInst machInst); 208 %(BasicExecDeclare)s 209 %(InitiateAccDeclare)s 210 %(CompleteAccDeclare)s 211 }; 212 213 class %(class_name)s_5 : public %(base_class)sMicro 214 { 215 public: | 203 %(class_name)s_4(ExtMachInst machInst); 204 %(BasicExecDeclare)s 205 %(InitiateAccDeclare)s 206 %(CompleteAccDeclare)s 207 }; 208 209 class %(class_name)s_5 : public %(base_class)sMicro 210 { 211 public: |
216 //Constructor | 212 // Constructor |
217 %(class_name)s_5(ExtMachInst machInst); 218 %(BasicExecDeclare)s 219 %(InitiateAccDeclare)s 220 %(CompleteAccDeclare)s 221 }; 222 223 class %(class_name)s_6 : public %(base_class)sMicro 224 { 225 public: | 213 %(class_name)s_5(ExtMachInst machInst); 214 %(BasicExecDeclare)s 215 %(InitiateAccDeclare)s 216 %(CompleteAccDeclare)s 217 }; 218 219 class %(class_name)s_6 : public %(base_class)sMicro 220 { 221 public: |
226 //Constructor | 222 // Constructor |
227 %(class_name)s_6(ExtMachInst machInst); 228 %(BasicExecDeclare)s 229 %(InitiateAccDeclare)s 230 %(CompleteAccDeclare)s 231 }; 232 233 class %(class_name)s_7 : public %(base_class)sMicro 234 { 235 public: | 223 %(class_name)s_6(ExtMachInst machInst); 224 %(BasicExecDeclare)s 225 %(InitiateAccDeclare)s 226 %(CompleteAccDeclare)s 227 }; 228 229 class %(class_name)s_7 : public %(base_class)sMicro 230 { 231 public: |
236 //Constructor | 232 // Constructor |
237 %(class_name)s_7(ExtMachInst machInst); 238 %(BasicExecDeclare)s 239 %(InitiateAccDeclare)s 240 %(CompleteAccDeclare)s 241 }; 242 }; 243}}; 244 --- 101 unchanged lines hidden --- | 233 %(class_name)s_7(ExtMachInst machInst); 234 %(BasicExecDeclare)s 235 %(InitiateAccDeclare)s 236 %(CompleteAccDeclare)s 237 }; 238 }; 239}}; 240 --- 101 unchanged lines hidden --- |