blockmem.isa (4539:6eeeea62b7c4) blockmem.isa (4648:173a212f5091)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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243}};
244
245// Basic instruction class constructor template.
246def template BlockMemConstructor {{
247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
248 : %(base_class)s("%(mnemonic)s", machInst)
249 {
250 %(constructor)s;
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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243}};
244
245// Basic instruction class constructor template.
246def template BlockMemConstructor {{
247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
248 : %(base_class)s("%(mnemonic)s", machInst)
249 {
250 %(constructor)s;
251 microops[0] = new %(class_name)s_0(machInst);
252 microops[1] = new %(class_name)s_1(machInst);
253 microops[2] = new %(class_name)s_2(machInst);
254 microops[3] = new %(class_name)s_3(machInst);
255 microops[4] = new %(class_name)s_4(machInst);
256 microops[5] = new %(class_name)s_5(machInst);
257 microops[6] = new %(class_name)s_6(machInst);
258 microops[7] = new %(class_name)s_7(machInst);
251 microOps[0] = new %(class_name)s_0(machInst);
252 microOps[1] = new %(class_name)s_1(machInst);
253 microOps[2] = new %(class_name)s_2(machInst);
254 microOps[3] = new %(class_name)s_3(machInst);
255 microOps[4] = new %(class_name)s_4(machInst);
256 microOps[5] = new %(class_name)s_5(machInst);
257 microOps[6] = new %(class_name)s_6(machInst);
258 microOps[7] = new %(class_name)s_7(machInst);
259 }
260}};
261
262def template BlockMemMicroConstructor {{
263 inline %(class_name)s::
264 %(class_name)s_%(micro_pc)s::
265 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",

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284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
286 decode_block = ROrImmDecode.subst(iop)
287 matcher = re.compile(r'Frd_N')
288 exec_output = ''
289 for microPc in range(8):
290 flag_code = ''
291 if (microPc == 7):
259 }
260}};
261
262def template BlockMemMicroConstructor {{
263 inline %(class_name)s::
264 %(class_name)s_%(micro_pc)s::
265 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",

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284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
286 decode_block = ROrImmDecode.subst(iop)
287 matcher = re.compile(r'Frd_N')
288 exec_output = ''
289 for microPc in range(8):
290 flag_code = ''
291 if (microPc == 7):
292 flag_code = "flags[IsLastMicroop] = true;"
292 flag_code = "flags[IsLastMicroOp] = true;"
293 elif (microPc == 0):
293 elif (microPc == 0):
294 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;"
294 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
295 else:
296 flag_code = "flags[IsDelayedCommit] = true;"
297 pcedCode = matcher.sub("Frd_%d" % microPc, code)
298 iop = InstObjParams(name, Name, 'BlockMem',
299 {"code": pcedCode, "ea_code": addrCalcReg,
300 "fault_check": faultCode, "micro_pc": microPc,
295 else:
296 flag_code = "flags[IsDelayedCommit] = true;"
297 pcedCode = matcher.sub("Frd_%d" % microPc, code)
298 iop = InstObjParams(name, Name, 'BlockMem',
299 {"code": pcedCode, "ea_code": addrCalcReg,
300 "fault_check": faultCode, "micro_pc": microPc,
301 "set_flags": flag_code}, opt_flags)
301 "set_flags": flag_code, "EA_trunc" : TruncateEA},
302 opt_flags)
302 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm',
303 {"code": pcedCode, "ea_code": addrCalcImm,
304 "fault_check": faultCode, "micro_pc": microPc,
303 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm',
304 {"code": pcedCode, "ea_code": addrCalcImm,
305 "fault_check": faultCode, "micro_pc": microPc,
305 "set_flags": flag_code}, opt_flags)
306 "set_flags": flag_code, "EA_trunc" : TruncateEA},
307 opt_flags)
306 decoder_output += BlockMemMicroConstructor.subst(iop)
307 decoder_output += BlockMemMicroConstructor.subst(iop_imm)
308 exec_output += doDualSplitExecute(
309 pcedCode, '', addrCalcReg, addrCalcImm, execute, faultCode,
310 makeMicroName(name, microPc),
311 makeMicroName(name + "Imm", microPc),
312 makeMicroName(Name, microPc),
313 makeMicroName(Name + "Imm", microPc),

--- 30 unchanged lines hidden --- 		308 decoder_output += BlockMemMicroConstructor.subst(iop)
309 decoder_output += BlockMemMicroConstructor.subst(iop_imm)
310 exec_output += doDualSplitExecute(
311 pcedCode, '', addrCalcReg, addrCalcImm, execute, faultCode,
312 makeMicroName(name, microPc),
313 makeMicroName(name + "Imm", microPc),
314 makeMicroName(Name, microPc),
315 makeMicroName(Name + "Imm", microPc),

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