| blockmem.isa (4362:95e5f28ce484) | blockmem.isa (4539:6eeeea62b7c4) |
|---|---|
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 234 unchanged lines hidden (view full) --- 243}}; 244 245// Basic instruction class constructor template. 246def template BlockMemConstructor {{ 247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 248 : %(base_class)s("%(mnemonic)s", machInst) 249 { 250 %(constructor)s; | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 234 unchanged lines hidden (view full) --- 243}}; 244 245// Basic instruction class constructor template. 246def template BlockMemConstructor {{ 247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 248 : %(base_class)s("%(mnemonic)s", machInst) 249 { 250 %(constructor)s; |
| 251 microOps[0] = new %(class_name)s_0(machInst); 252 microOps[1] = new %(class_name)s_1(machInst); 253 microOps[2] = new %(class_name)s_2(machInst); 254 microOps[3] = new %(class_name)s_3(machInst); 255 microOps[4] = new %(class_name)s_4(machInst); 256 microOps[5] = new %(class_name)s_5(machInst); 257 microOps[6] = new %(class_name)s_6(machInst); 258 microOps[7] = new %(class_name)s_7(machInst); | 251 microops[0] = new %(class_name)s_0(machInst); 252 microops[1] = new %(class_name)s_1(machInst); 253 microops[2] = new %(class_name)s_2(machInst); 254 microops[3] = new %(class_name)s_3(machInst); 255 microops[4] = new %(class_name)s_4(machInst); 256 microops[5] = new %(class_name)s_5(machInst); 257 microops[6] = new %(class_name)s_6(machInst); 258 microops[7] = new %(class_name)s_7(machInst); |
| 259 } 260}}; 261 262def template BlockMemMicroConstructor {{ 263 inline %(class_name)s:: 264 %(class_name)s_%(micro_pc)s:: 265 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) : 266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", --- 17 unchanged lines hidden (view full) --- 284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 286 decode_block = ROrImmDecode.subst(iop) 287 matcher = re.compile(r'Frd_N') 288 exec_output = '' 289 for microPc in range(8): 290 flag_code = '' 291 if (microPc == 7): | 259 } 260}}; 261 262def template BlockMemMicroConstructor {{ 263 inline %(class_name)s:: 264 %(class_name)s_%(micro_pc)s:: 265 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) : 266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", --- 17 unchanged lines hidden (view full) --- 284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 286 decode_block = ROrImmDecode.subst(iop) 287 matcher = re.compile(r'Frd_N') 288 exec_output = '' 289 for microPc in range(8): 290 flag_code = '' 291 if (microPc == 7): |
| 292 flag_code = "flags[IsLastMicroOp] = true;" | 292 flag_code = "flags[IsLastMicroop] = true;" |
| 293 elif (microPc == 0): | 293 elif (microPc == 0): |
| 294 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" | 294 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" |
| 295 else: 296 flag_code = "flags[IsDelayedCommit] = true;" 297 pcedCode = matcher.sub("Frd_%d" % microPc, code) 298 iop = InstObjParams(name, Name, 'BlockMem', 299 {"code": pcedCode, "ea_code": addrCalcReg, 300 "fault_check": faultCode, "micro_pc": microPc, 301 "set_flags": flag_code}, opt_flags) 302 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', --- 41 unchanged lines hidden --- | 295 else: 296 flag_code = "flags[IsDelayedCommit] = true;" 297 pcedCode = matcher.sub("Frd_%d" % microPc, code) 298 iop = InstObjParams(name, Name, 'BlockMem', 299 {"code": pcedCode, "ea_code": addrCalcReg, 300 "fault_check": faultCode, "micro_pc": microPc, 301 "set_flags": flag_code}, opt_flags) 302 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', --- 41 unchanged lines hidden --- |