1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 152 unchanged lines hidden (view full) --- 161 162 protected: 163 class %(class_name)s_0 : public %(base_class)sMicro 164 { 165 public: 166 //Constructor 167 %(class_name)s_0(ExtMachInst machInst); 168 %(BasicExecDeclare)s |
169 %(InitiateAccDeclare)s 170 %(CompleteAccDeclare)s |
171 }; 172 173 class %(class_name)s_1 : public %(base_class)sMicro 174 { 175 public: 176 //Constructor 177 %(class_name)s_1(ExtMachInst machInst); 178 %(BasicExecDeclare)s |
179 %(InitiateAccDeclare)s 180 %(CompleteAccDeclare)s |
181 }; 182 183 class %(class_name)s_2 : public %(base_class)sMicro 184 { 185 public: 186 //Constructor 187 %(class_name)s_2(ExtMachInst machInst); 188 %(BasicExecDeclare)s |
189 %(InitiateAccDeclare)s 190 %(CompleteAccDeclare)s |
191 }; 192 193 class %(class_name)s_3 : public %(base_class)sMicro 194 { 195 public: 196 //Constructor 197 %(class_name)s_3(ExtMachInst machInst); 198 %(BasicExecDeclare)s |
199 %(InitiateAccDeclare)s 200 %(CompleteAccDeclare)s |
201 }; 202 203 class %(class_name)s_4 : public %(base_class)sMicro 204 { 205 public: 206 //Constructor 207 %(class_name)s_4(ExtMachInst machInst); 208 %(BasicExecDeclare)s |
209 %(InitiateAccDeclare)s 210 %(CompleteAccDeclare)s |
211 }; 212 213 class %(class_name)s_5 : public %(base_class)sMicro 214 { 215 public: 216 //Constructor 217 %(class_name)s_5(ExtMachInst machInst); 218 %(BasicExecDeclare)s |
219 %(InitiateAccDeclare)s 220 %(CompleteAccDeclare)s |
221 }; 222 223 class %(class_name)s_6 : public %(base_class)sMicro 224 { 225 public: 226 //Constructor 227 %(class_name)s_6(ExtMachInst machInst); 228 %(BasicExecDeclare)s |
229 %(InitiateAccDeclare)s 230 %(CompleteAccDeclare)s |
231 }; 232 233 class %(class_name)s_7 : public %(base_class)sMicro 234 { 235 public: 236 //Constructor 237 %(class_name)s_7(ExtMachInst machInst); 238 %(BasicExecDeclare)s |
239 %(InitiateAccDeclare)s 240 %(CompleteAccDeclare)s |
241 }; 242 }; 243}}; 244 245// Basic instruction class constructor template. 246def template BlockMemConstructor {{ 247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 248 : %(base_class)s("%(mnemonic)s", machInst) --- 17 unchanged lines hidden (view full) --- 266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", 267 machInst, %(op_class)s, %(micro_pc)s * 8) 268 { 269 %(constructor)s; 270 %(set_flags)s; 271 } 272}}; 273 |
274let {{ 275 |
276 def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): |
277 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 278 # are split into ones that are available in priv and hpriv, and 279 # those that are only available in hpriv |
280 addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 281 addrCalcImm = 'EA = Rs1 + imm + offset;' 282 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) 283 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) 284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 286 decode_block = ROrImmDecode.subst(iop) 287 matcher = re.compile(r'Frd_N') 288 exec_output = '' |
289 for microPc in range(8): |
290 flag_code = '' |
291 if (microPc == 7): |
292 flag_code = "flags[IsLastMicroOp] = true;" |
293 pcedCode = matcher.sub("Frd_%d" % microPc, code) |
294 iop = InstObjParams(name, Name, 'BlockMem', pcedCode, 295 opt_flags, {"ea_code": addrCalcReg, |
296 "fault_check": faultCode, "micro_pc": microPc, |
297 "set_flags": flag_code}) 298 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode, 299 opt_flags, {"ea_code": addrCalcImm, |
300 "fault_check": faultCode, "micro_pc": microPc, |
301 "set_flags": flag_code}) |
302 decoder_output += BlockMemMicroConstructor.subst(iop) 303 decoder_output += BlockMemMicroConstructor.subst(iop_imm) |
304 exec_output += doSplitExecute( 305 pcedCode, addrCalcReg, addrCalcImm, execute, faultCode, 306 makeMicroName(name, microPc), 307 makeMicroName(name + "Imm", microPc), 308 makeMicroName(Name, microPc), 309 makeMicroName(Name + "Imm", microPc), 310 opt_flags); 311 faultCode = '' |
312 return (header_output, decoder_output, exec_output, decode_block) 313}}; 314 315def format BlockLoad(code, *opt_flags) {{ |
316 # We need to make sure to check the highest priority fault last. 317 # That way, if other faults have been detected, they'll be overwritten 318 # rather than the other way around. 319 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck |
320 (header_output, 321 decoder_output, 322 exec_output, |
323 decode_block) = doBlockMemFormat(code, faultCode, 324 LoadExecute, name, Name, opt_flags) |
325}}; 326 327def format BlockStore(code, *opt_flags) {{ |
328 # We need to make sure to check the highest priority fault last. 329 # That way, if other faults have been detected, they'll be overwritten 330 # rather than the other way around. 331 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck |
332 (header_output, 333 decoder_output, 334 exec_output, |
335 decode_block) = doBlockMemFormat(code, faultCode, 336 StoreExecute, name, Name, opt_flags) |
337}}; |