blockmem.isa (3388:1c6ebfc4c20e) | blockmem.isa (3391:3b6298cab636) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 152 unchanged lines hidden (view full) --- 161 162 protected: 163 class %(class_name)s_0 : public %(base_class)sMicro 164 { 165 public: 166 //Constructor 167 %(class_name)s_0(ExtMachInst machInst); 168 %(BasicExecDeclare)s | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 152 unchanged lines hidden (view full) --- 161 162 protected: 163 class %(class_name)s_0 : public %(base_class)sMicro 164 { 165 public: 166 //Constructor 167 %(class_name)s_0(ExtMachInst machInst); 168 %(BasicExecDeclare)s |
169 %(InitiateAccDeclare)s 170 %(CompleteAccDeclare)s |
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169 }; 170 171 class %(class_name)s_1 : public %(base_class)sMicro 172 { 173 public: 174 //Constructor 175 %(class_name)s_1(ExtMachInst machInst); 176 %(BasicExecDeclare)s | 171 }; 172 173 class %(class_name)s_1 : public %(base_class)sMicro 174 { 175 public: 176 //Constructor 177 %(class_name)s_1(ExtMachInst machInst); 178 %(BasicExecDeclare)s |
179 %(InitiateAccDeclare)s 180 %(CompleteAccDeclare)s |
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177 }; 178 179 class %(class_name)s_2 : public %(base_class)sMicro 180 { 181 public: 182 //Constructor 183 %(class_name)s_2(ExtMachInst machInst); 184 %(BasicExecDeclare)s | 181 }; 182 183 class %(class_name)s_2 : public %(base_class)sMicro 184 { 185 public: 186 //Constructor 187 %(class_name)s_2(ExtMachInst machInst); 188 %(BasicExecDeclare)s |
189 %(InitiateAccDeclare)s 190 %(CompleteAccDeclare)s |
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185 }; 186 187 class %(class_name)s_3 : public %(base_class)sMicro 188 { 189 public: 190 //Constructor 191 %(class_name)s_3(ExtMachInst machInst); 192 %(BasicExecDeclare)s | 191 }; 192 193 class %(class_name)s_3 : public %(base_class)sMicro 194 { 195 public: 196 //Constructor 197 %(class_name)s_3(ExtMachInst machInst); 198 %(BasicExecDeclare)s |
199 %(InitiateAccDeclare)s 200 %(CompleteAccDeclare)s |
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193 }; 194 195 class %(class_name)s_4 : public %(base_class)sMicro 196 { 197 public: 198 //Constructor 199 %(class_name)s_4(ExtMachInst machInst); 200 %(BasicExecDeclare)s | 201 }; 202 203 class %(class_name)s_4 : public %(base_class)sMicro 204 { 205 public: 206 //Constructor 207 %(class_name)s_4(ExtMachInst machInst); 208 %(BasicExecDeclare)s |
209 %(InitiateAccDeclare)s 210 %(CompleteAccDeclare)s |
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201 }; 202 203 class %(class_name)s_5 : public %(base_class)sMicro 204 { 205 public: 206 //Constructor 207 %(class_name)s_5(ExtMachInst machInst); 208 %(BasicExecDeclare)s | 211 }; 212 213 class %(class_name)s_5 : public %(base_class)sMicro 214 { 215 public: 216 //Constructor 217 %(class_name)s_5(ExtMachInst machInst); 218 %(BasicExecDeclare)s |
219 %(InitiateAccDeclare)s 220 %(CompleteAccDeclare)s |
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209 }; 210 211 class %(class_name)s_6 : public %(base_class)sMicro 212 { 213 public: 214 //Constructor 215 %(class_name)s_6(ExtMachInst machInst); 216 %(BasicExecDeclare)s | 221 }; 222 223 class %(class_name)s_6 : public %(base_class)sMicro 224 { 225 public: 226 //Constructor 227 %(class_name)s_6(ExtMachInst machInst); 228 %(BasicExecDeclare)s |
229 %(InitiateAccDeclare)s 230 %(CompleteAccDeclare)s |
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217 }; 218 219 class %(class_name)s_7 : public %(base_class)sMicro 220 { 221 public: 222 //Constructor 223 %(class_name)s_7(ExtMachInst machInst); 224 %(BasicExecDeclare)s | 231 }; 232 233 class %(class_name)s_7 : public %(base_class)sMicro 234 { 235 public: 236 //Constructor 237 %(class_name)s_7(ExtMachInst machInst); 238 %(BasicExecDeclare)s |
239 %(InitiateAccDeclare)s 240 %(CompleteAccDeclare)s |
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225 }; 226 }; 227}}; 228 229// Basic instruction class constructor template. 230def template BlockMemConstructor {{ 231 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 232 : %(base_class)s("%(mnemonic)s", machInst) --- 17 unchanged lines hidden (view full) --- 250 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", 251 machInst, %(op_class)s, %(micro_pc)s * 8) 252 { 253 %(constructor)s; 254 %(set_flags)s; 255 } 256}}; 257 | 241 }; 242 }; 243}}; 244 245// Basic instruction class constructor template. 246def template BlockMemConstructor {{ 247 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 248 : %(base_class)s("%(mnemonic)s", machInst) --- 17 unchanged lines hidden (view full) --- 266 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", 267 machInst, %(op_class)s, %(micro_pc)s * 8) 268 { 269 %(constructor)s; 270 %(set_flags)s; 271 } 272}}; 273 |
258def template MicroLoadExecute {{ 259 Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute( 260 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 261 { 262 Fault fault = NoFault; 263 Addr EA; 264 %(op_decl)s; 265 %(op_rd)s; 266 %(ea_code)s; 267 %(fault_check)s; 268 DPRINTF(Sparc, "The address is 0x%x\n", EA); 269 xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); 270 %(code)s; 271 272 if(fault == NoFault) 273 { 274 //Write the resulting state to the execution context 275 %(op_wb)s; 276 } 277 278 return fault; 279 } 280}}; 281 282def template MicroStoreExecute {{ 283 Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute( 284 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 285 { 286 Fault fault = NoFault; 287 uint64_t write_result = 0; 288 Addr EA; 289 %(op_decl)s; 290 %(op_rd)s; 291 %(ea_code)s; 292 %(fault_check)s; 293 DPRINTF(Sparc, "The address is 0x%x\n", EA); 294 %(code)s; 295 296 if(fault == NoFault) 297 { 298 xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); 299 //Write the resulting state to the execution context 300 %(op_wb)s; 301 } 302 303 return fault; 304 } 305}}; 306 | |
307let {{ 308 | 274let {{ 275 |
309 def doBlockMemFormat(code, execute, name, Name, opt_flags): | 276 def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): |
310 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 311 # are split into ones that are available in priv and hpriv, and 312 # those that are only available in hpriv | 277 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 278 # are split into ones that are available in priv and hpriv, and 279 # those that are only available in hpriv |
313 faultCheck = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0) 314 return new PrivilegedAction; 315 if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 316 return new PrivilegedAction; 317 //The LSB can be zero, since it's really the MSB in doubles 318 //and quads 319 if(RD & 0xe) 320 return new IllegalInstruction; 321 if(EA & 0x3f) 322 return new MemAddressNotAligned; 323 ''' | |
324 addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 325 addrCalcImm = 'EA = Rs1 + imm + offset;' 326 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) 327 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) 328 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 329 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 330 decode_block = ROrImmDecode.subst(iop) 331 matcher = re.compile(r'Frd_N') 332 exec_output = '' | 280 addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 281 addrCalcImm = 'EA = Rs1 + imm + offset;' 282 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) 283 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) 284 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 285 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 286 decode_block = ROrImmDecode.subst(iop) 287 matcher = re.compile(r'Frd_N') 288 exec_output = '' |
333 for microPC in range(8): | 289 for microPc in range(8): |
334 flag_code = '' | 290 flag_code = '' |
335 if (microPC == 7): | 291 if (microPc == 7): |
336 flag_code = "flags[IsLastMicroOp] = true;" | 292 flag_code = "flags[IsLastMicroOp] = true;" |
337 pcedCode = matcher.sub("Frd_%d" % microPC, code) | 293 pcedCode = matcher.sub("Frd_%d" % microPc, code) |
338 iop = InstObjParams(name, Name, 'BlockMem', pcedCode, 339 opt_flags, {"ea_code": addrCalcReg, | 294 iop = InstObjParams(name, Name, 'BlockMem', pcedCode, 295 opt_flags, {"ea_code": addrCalcReg, |
340 "fault_check": faultCheck, "micro_pc": microPC, | 296 "fault_check": faultCode, "micro_pc": microPc, |
341 "set_flags": flag_code}) 342 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode, 343 opt_flags, {"ea_code": addrCalcImm, | 297 "set_flags": flag_code}) 298 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode, 299 opt_flags, {"ea_code": addrCalcImm, |
344 "fault_check": faultCheck, "micro_pc": microPC, | 300 "fault_check": faultCode, "micro_pc": microPc, |
345 "set_flags": flag_code}) | 301 "set_flags": flag_code}) |
346 exec_output += execute.subst(iop) 347 exec_output += execute.subst(iop_imm) | |
348 decoder_output += BlockMemMicroConstructor.subst(iop) 349 decoder_output += BlockMemMicroConstructor.subst(iop_imm) | 302 decoder_output += BlockMemMicroConstructor.subst(iop) 303 decoder_output += BlockMemMicroConstructor.subst(iop_imm) |
350 faultCheck = '' | 304 exec_output += doSplitExecute( 305 pcedCode, addrCalcReg, addrCalcImm, execute, faultCode, 306 makeMicroName(name, microPc), 307 makeMicroName(name + "Imm", microPc), 308 makeMicroName(Name, microPc), 309 makeMicroName(Name + "Imm", microPc), 310 opt_flags); 311 faultCode = '' |
351 return (header_output, decoder_output, exec_output, decode_block) 352}}; 353 354def format BlockLoad(code, *opt_flags) {{ | 312 return (header_output, decoder_output, exec_output, decode_block) 313}}; 314 315def format BlockLoad(code, *opt_flags) {{ |
316 # We need to make sure to check the highest priority fault last. 317 # That way, if other faults have been detected, they'll be overwritten 318 # rather than the other way around. 319 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck |
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355 (header_output, 356 decoder_output, 357 exec_output, | 320 (header_output, 321 decoder_output, 322 exec_output, |
358 decode_block) = doBlockMemFormat(code, MicroLoadExecute, 359 name, Name, opt_flags) | 323 decode_block) = doBlockMemFormat(code, faultCode, 324 LoadExecute, name, Name, opt_flags) |
360}}; 361 362def format BlockStore(code, *opt_flags) {{ | 325}}; 326 327def format BlockStore(code, *opt_flags) {{ |
328 # We need to make sure to check the highest priority fault last. 329 # That way, if other faults have been detected, they'll be overwritten 330 # rather than the other way around. 331 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck |
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363 (header_output, 364 decoder_output, 365 exec_output, | 332 (header_output, 333 decoder_output, 334 exec_output, |
366 decode_block) = doBlockMemFormat(code, MicroStoreExecute, 367 name, Name, opt_flags) | 335 decode_block) = doBlockMemFormat(code, faultCode, 336 StoreExecute, name, Name, opt_flags) |
368}}; | 337}}; |