1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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95 std::string BlockMemMicro::generateDisassembly(Addr pc,
96 const SymbolTable *symtab) const
97 {
98 std::stringstream response;
99 bool load = flags[IsLoad];
100 bool save = flags[IsStore];
101
102 printMnemonic(response, mnemonic);
103 if(save)
104 {
105 printReg(response, _srcRegIdx[0]);
106 ccprintf(response, ", ");
107 }
108 ccprintf(response, "[ ");
109 printReg(response, _srcRegIdx[!save ? 0 : 1]);
110 ccprintf(response, " + ");
111 printReg(response, _srcRegIdx[!save ? 1 : 2]);
112 ccprintf(response, " ]");
113 if(load)
114 {
115 ccprintf(response, ", ");
116 printReg(response, _destRegIdx[0]);
117 }
118
119 return response.str();
120 }
121
122 std::string BlockMemImmMicro::generateDisassembly(Addr pc,
123 const SymbolTable *symtab) const
124 {
125 std::stringstream response;
126 bool load = flags[IsLoad];
127 bool save = flags[IsStore];
128
129 printMnemonic(response, mnemonic);
130 if(save)
131 {
132 printReg(response, _srcRegIdx[1]);
133 ccprintf(response, ", ");
134 }
135 ccprintf(response, "[ ");
136 printReg(response, _srcRegIdx[0]);
137 if(imm >= 0)
138 ccprintf(response, " + 0x%x ]", imm);
139 else
140 ccprintf(response, " + -0x%x ]", -imm);
141 if(load)
142 {
143 ccprintf(response, ", ");
144 printReg(response, _destRegIdx[0]);
145 }
146
147 return response.str();
148 }
149
150}};
151
152def template BlockMemDeclare {{
153 /**
154 * Static instruction class for a block memory operation
155 */
156 class %(class_name)s : public %(base_class)s
157 {
158 public:
159 //Constructor
160 %(class_name)s(ExtMachInst machInst);
161
162 protected:
163 class %(class_name)s_0 : public %(base_class)sMicro
164 {
165 public:
166 //Constructor
167 %(class_name)s_0(ExtMachInst machInst);
168 %(BasicExecDeclare)s
169 %(InitiateAccDeclare)s
170 %(CompleteAccDeclare)s
171 };
172
173 class %(class_name)s_1 : public %(base_class)sMicro
174 {
175 public:
176 //Constructor
177 %(class_name)s_1(ExtMachInst machInst);
178 %(BasicExecDeclare)s
179 %(InitiateAccDeclare)s
180 %(CompleteAccDeclare)s
181 };
182
183 class %(class_name)s_2 : public %(base_class)sMicro
184 {
185 public:
186 //Constructor
187 %(class_name)s_2(ExtMachInst machInst);
188 %(BasicExecDeclare)s
189 %(InitiateAccDeclare)s
190 %(CompleteAccDeclare)s
191 };
192
193 class %(class_name)s_3 : public %(base_class)sMicro
194 {
195 public:
196 //Constructor
197 %(class_name)s_3(ExtMachInst machInst);
198 %(BasicExecDeclare)s
199 %(InitiateAccDeclare)s
200 %(CompleteAccDeclare)s
201 };
202
203 class %(class_name)s_4 : public %(base_class)sMicro
204 {
205 public:
206 //Constructor
207 %(class_name)s_4(ExtMachInst machInst);
208 %(BasicExecDeclare)s
209 %(InitiateAccDeclare)s
210 %(CompleteAccDeclare)s
211 };
212
213 class %(class_name)s_5 : public %(base_class)sMicro
214 {
215 public:
216 //Constructor
217 %(class_name)s_5(ExtMachInst machInst);
218 %(BasicExecDeclare)s
219 %(InitiateAccDeclare)s
220 %(CompleteAccDeclare)s
221 };
222
223 class %(class_name)s_6 : public %(base_class)sMicro
224 {
225 public:
226 //Constructor
227 %(class_name)s_6(ExtMachInst machInst);
228 %(BasicExecDeclare)s
229 %(InitiateAccDeclare)s
230 %(CompleteAccDeclare)s
231 };
232
233 class %(class_name)s_7 : public %(base_class)sMicro
234 {
235 public:
236 //Constructor
237 %(class_name)s_7(ExtMachInst machInst);
238 %(BasicExecDeclare)s
239 %(InitiateAccDeclare)s
240 %(CompleteAccDeclare)s
241 };
242 };
243}};
244

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