1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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161
162 protected:
163 class %(class_name)s_0 : public %(base_class)sMicro
164 {
165 public:
166 //Constructor
167 %(class_name)s_0(ExtMachInst machInst);
168 %(BasicExecDeclare)s
169 };
170
171 class %(class_name)s_1 : public %(base_class)sMicro
172 {
173 public:
174 //Constructor
175 %(class_name)s_1(ExtMachInst machInst);
176 %(BasicExecDeclare)s
177 };
178
179 class %(class_name)s_2 : public %(base_class)sMicro
180 {
181 public:
182 //Constructor
183 %(class_name)s_2(ExtMachInst machInst);
184 %(BasicExecDeclare)s
185 };
186
187 class %(class_name)s_3 : public %(base_class)sMicro
188 {
189 public:
190 //Constructor
191 %(class_name)s_3(ExtMachInst machInst);
192 %(BasicExecDeclare)s
193 };
194
195 class %(class_name)s_4 : public %(base_class)sMicro
196 {
197 public:
198 //Constructor
199 %(class_name)s_4(ExtMachInst machInst);
200 %(BasicExecDeclare)s
201 };
202
203 class %(class_name)s_5 : public %(base_class)sMicro
204 {
205 public:
206 //Constructor
207 %(class_name)s_5(ExtMachInst machInst);
208 %(BasicExecDeclare)s
209 };
210
211 class %(class_name)s_6 : public %(base_class)sMicro
212 {
213 public:
214 //Constructor
215 %(class_name)s_6(ExtMachInst machInst);
216 %(BasicExecDeclare)s
217 };
218
219 class %(class_name)s_7 : public %(base_class)sMicro
220 {
221 public:
222 //Constructor
223 %(class_name)s_7(ExtMachInst machInst);
224 %(BasicExecDeclare)s
225 };
226 };
227}};
228
229// Basic instruction class constructor template.
230def template BlockMemConstructor {{
231 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
232 : %(base_class)s("%(mnemonic)s", machInst)

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250 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
251 machInst, %(op_class)s, %(micro_pc)s * 8)
252 {
253 %(constructor)s;
254 %(set_flags)s;
255 }
256}};
257
258def template MicroLoadExecute {{
259 Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
260 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
261 {
262 Fault fault = NoFault;
263 Addr EA;
264 %(op_decl)s;
265 %(op_rd)s;
266 %(ea_code)s;
267 %(fault_check)s;
268 DPRINTF(Sparc, "The address is 0x%x\n", EA);
269 xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
270 %(code)s;
271
272 if(fault == NoFault)
273 {
274 //Write the resulting state to the execution context
275 %(op_wb)s;
276 }
277
278 return fault;
279 }
280}};
281
282def template MicroStoreExecute {{
283 Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
284 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
285 {
286 Fault fault = NoFault;
287 uint64_t write_result = 0;
288 Addr EA;
289 %(op_decl)s;
290 %(op_rd)s;
291 %(ea_code)s;
292 %(fault_check)s;
293 DPRINTF(Sparc, "The address is 0x%x\n", EA);
294 %(code)s;
295
296 if(fault == NoFault)
297 {
298 xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
299 //Write the resulting state to the execution context
300 %(op_wb)s;
301 }
302
303 return fault;
304 }
305}};
306
307let {{
308
309 def doBlockMemFormat(code, execute, name, Name, opt_flags):
310 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
311 # are split into ones that are available in priv and hpriv, and
312 # those that are only available in hpriv
313 faultCheck = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
314 return new PrivilegedAction;
315 if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
316 return new PrivilegedAction;
317 //The LSB can be zero, since it's really the MSB in doubles
318 //and quads
319 if(RD & 0xe)
320 return new IllegalInstruction;
321 if(EA & 0x3f)
322 return new MemAddressNotAligned;
323 '''
324 addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
325 addrCalcImm = 'EA = Rs1 + imm + offset;'
326 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
327 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
328 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
329 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
330 decode_block = ROrImmDecode.subst(iop)
331 matcher = re.compile(r'Frd_N')
332 exec_output = ''
333 for microPC in range(8):
334 flag_code = ''
335 if (microPC == 7):
336 flag_code = "flags[IsLastMicroOp] = true;"
337 pcedCode = matcher.sub("Frd_%d" % microPC, code)
338 iop = InstObjParams(name, Name, 'BlockMem', pcedCode,
339 opt_flags, {"ea_code": addrCalcReg,
340 "fault_check": faultCheck, "micro_pc": microPC,
341 "set_flags": flag_code})
342 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode,
343 opt_flags, {"ea_code": addrCalcImm,
344 "fault_check": faultCheck, "micro_pc": microPC,
345 "set_flags": flag_code})
346 exec_output += execute.subst(iop)
347 exec_output += execute.subst(iop_imm)
348 decoder_output += BlockMemMicroConstructor.subst(iop)
349 decoder_output += BlockMemMicroConstructor.subst(iop_imm)
350 faultCheck = ''
351 return (header_output, decoder_output, exec_output, decode_block)
352}};
353
354def format BlockLoad(code, *opt_flags) {{
355 (header_output,
356 decoder_output,
357 exec_output,
358 decode_block) = doBlockMemFormat(code, MicroLoadExecute,
359 name, Name, opt_flags)
360}};
361
362def format BlockStore(code, *opt_flags) {{
363 (header_output,
364 decoder_output,
365 exec_output,
366 decode_block) = doBlockMemFormat(code, MicroStoreExecute,
367 name, Name, opt_flags)
368}};