basicmem.isa (3950:19a99edda63b) basicmem.isa (4040:eb894f3fc168)
1// Copyright (c) 2006 The Regents of The University of Michigan
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the

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47
48 %(InitiateAccDeclare)s
49
50 %(CompleteAccDeclare)s
51 };
52}};
53
54let {{
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the

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47
48 %(InitiateAccDeclare)s
49
50 %(CompleteAccDeclare)s
51 };
52}};
53
54let {{
55 def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags):
55 def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
56 addrCalcReg = 'EA = Rs1 + Rs2;'
57 addrCalcImm = 'EA = Rs1 + imm;'
58 iop = InstObjParams(name, Name, 'Mem',
56 addrCalcReg = 'EA = Rs1 + Rs2;'
57 addrCalcImm = 'EA = Rs1 + imm;'
58 iop = InstObjParams(name, Name, 'Mem',
59 {"code": code, "fault_check": faultCode,
60 "ea_code": addrCalcReg},
61 opt_flags)
59 {"code": code, "postacc_code" : postacc_code,
60 "fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags)
62 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
61 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
63 {"code": code, "fault_check": faultCode,
64 "ea_code": addrCalcImm},
65 opt_flags)
62 {"code": code, "postacc_code" : postacc_code,
63 "fault_check": faultCode, "ea_code": addrCalcImm}, opt_flags)
66 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
67 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
68 decode_block = ROrImmDecode.subst(iop)
64 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
65 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
66 decode_block = ROrImmDecode.subst(iop)
69 exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
70 execute, faultCode, name, name + "Imm",
67 exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
68 addrCalcImm, execute, faultCode, name, name + "Imm",
71 Name, Name + "Imm", asi, opt_flags)
72 return (header_output, decoder_output, exec_output, decode_block)
73}};
74
75def format LoadAlt(code, asi, *opt_flags) {{
76 (header_output,
77 decoder_output,
78 exec_output,

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98
99def format Store(code, *opt_flags) {{
100 (header_output,
101 decoder_output,
102 exec_output,
103 decode_block) = doMemFormat(code,
104 StoreFuncs, '', name, Name, 0, opt_flags)
105}};
69 Name, Name + "Imm", asi, opt_flags)
70 return (header_output, decoder_output, exec_output, decode_block)
71}};
72
73def format LoadAlt(code, asi, *opt_flags) {{
74 (header_output,
75 decoder_output,
76 exec_output,

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96
97def format Store(code, *opt_flags) {{
98 (header_output,
99 decoder_output,
100 exec_output,
101 decode_block) = doMemFormat(code,
102 StoreFuncs, '', name, Name, 0, opt_flags)
103}};
104
105def format TwinLoad(code, asi, *opt_flags) {{
106 (header_output,
107 decoder_output,
108 exec_output,
109 decode_block) = doMemFormat(code, LoadFuncs,
110 AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
111 name, Name, asi, opt_flags)
112}};
113