1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29
30////////////////////////////////////////////////////////////////////
31//
32// Mem instructions
33//
34
35def template MemDeclare {{
36 /**
37 * Static instruction class for "%(mnemonic)s".
38 */
39 class %(class_name)s : public %(base_class)s
40 {
41 public:
42
43 /// Constructor.
44 %(class_name)s(ExtMachInst machInst);
45
46 %(BasicExecDeclare)s
47
48 %(InitiateAccDeclare)s
49
50 %(CompleteAccDeclare)s
51 };
52}};
53
54let {{
55 def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
56 addrCalcReg = 'EA = Rs1 + Rs2;'
57 addrCalcImm = 'EA = Rs1 + imm;'
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29
30////////////////////////////////////////////////////////////////////
31//
32// Mem instructions
33//
34
35def template MemDeclare {{
36 /**
37 * Static instruction class for "%(mnemonic)s".
38 */
39 class %(class_name)s : public %(base_class)s
40 {
41 public:
42
43 /// Constructor.
44 %(class_name)s(ExtMachInst machInst);
45
46 %(BasicExecDeclare)s
47
48 %(InitiateAccDeclare)s
49
50 %(CompleteAccDeclare)s
51 };
52}};
53
54let {{
55 def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
56 addrCalcReg = 'EA = Rs1 + Rs2;'
57 addrCalcImm = 'EA = Rs1 + imm;'
|
58 iop = InstObjParams(name, Name, 'Mem', code,
59 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcReg})
60 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code,
61 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcImm})
| 58 iop = InstObjParams(name, Name, 'Mem',
59 {"code": code, "fault_check": faultCode,
60 "ea_code": addrCalcReg},
61 opt_flags)
62 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
63 {"code": code, "fault_check": faultCode,
64 "ea_code": addrCalcImm},
65 opt_flags)
|
62 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
63 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
64 decode_block = ROrImmDecode.subst(iop)
| 66 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
67 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
68 decode_block = ROrImmDecode.subst(iop)
|
65 exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, execute,
66 faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags)
| 69 exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
70 execute, faultCode, name, name + "Imm",
71 Name, Name + "Imm", opt_flags)
|
67 return (header_output, decoder_output, exec_output, decode_block)
68}};
69
70def format LoadAlt(code, *opt_flags) {{
71 (header_output,
72 decoder_output,
73 exec_output,
| 72 return (header_output, decoder_output, exec_output, decode_block)
73}};
74
75def format LoadAlt(code, *opt_flags) {{
76 (header_output,
77 decoder_output,
78 exec_output,
|
74 decode_block) = doMemFormat(code, LoadExecute,
| 79 decode_block) = doMemFormat(code, LoadFuncs,
|
75 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
76}};
77
78def format StoreAlt(code, *opt_flags) {{
79 (header_output,
80 decoder_output,
81 exec_output,
| 80 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
81}};
82
83def format StoreAlt(code, *opt_flags) {{
84 (header_output,
85 decoder_output,
86 exec_output,
|
82 decode_block) = doMemFormat(code, StoreExecute,
| 87 decode_block) = doMemFormat(code, StoreFuncs,
|
83 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
84}};
85
86def format Load(code, *opt_flags) {{
87 (header_output,
88 decoder_output,
89 exec_output,
90 decode_block) = doMemFormat(code,
| 88 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
89}};
90
91def format Load(code, *opt_flags) {{
92 (header_output,
93 decoder_output,
94 exec_output,
95 decode_block) = doMemFormat(code,
|
91 LoadExecute, '', name, Name, opt_flags)
| 96 LoadFuncs, '', name, Name, opt_flags)
|
92}};
93
94def format Store(code, *opt_flags) {{
95 (header_output,
96 decoder_output,
97 exec_output,
98 decode_block) = doMemFormat(code,
| 97}};
98
99def format Store(code, *opt_flags) {{
100 (header_output,
101 decoder_output,
102 exec_output,
103 decode_block) = doMemFormat(code,
|
99 StoreExecute, '', name, Name, opt_flags)
| 104 StoreFuncs, '', name, Name, opt_flags)
|
100}};
| 105}};
|