1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29
30////////////////////////////////////////////////////////////////////
31//
32// Mem instructions
33//
34
35output header {{
36 /**
37 * Base class for memory operations.
38 */
39 class Mem : public SparcStaticInst
40 {
41 protected:
42
43 // Constructor
44 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
45 SparcStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
49 std::string generateDisassembly(Addr pc,
50 const SymbolTable *symtab) const;
51 };
52
53 /**
54 * Class for memory operations which use an immediate offset.
55 */
56 class MemImm : public Mem
57 {
58 protected:
59
60 // Constructor
61 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
62 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
63 {}
64
65 std::string generateDisassembly(Addr pc,
66 const SymbolTable *symtab) const;
67
68 const int32_t imm;
69 };
70}};
71
72output decoder {{
73 std::string Mem::generateDisassembly(Addr pc,
74 const SymbolTable *symtab) const
75 {
76 std::stringstream response;
77 bool load = flags[IsLoad];
78 bool save = flags[IsStore];
79
80 printMnemonic(response, mnemonic);
81 if(save)
82 {
83 printReg(response, _srcRegIdx[0]);
84 ccprintf(response, ", ");
85 }
86 ccprintf(response, "[ ");
87 printReg(response, _srcRegIdx[!save ? 0 : 1]);
88 ccprintf(response, " + ");
89 printReg(response, _srcRegIdx[!save ? 1 : 2]);
90 ccprintf(response, " ]");
91 if(load)
92 {
93 ccprintf(response, ", ");
94 printReg(response, _destRegIdx[0]);
95 }
96
97 return response.str();
98 }
99
100 std::string MemImm::generateDisassembly(Addr pc,
101 const SymbolTable *symtab) const
102 {
103 std::stringstream response;
104 bool load = flags[IsLoad];
105 bool save = flags[IsStore];
106
107 printMnemonic(response, mnemonic);
108 if(save)
109 {
110 printReg(response, _srcRegIdx[0]);
111 ccprintf(response, ", ");
112 }
113 ccprintf(response, "[ ");
114 printReg(response, _srcRegIdx[!save ? 0 : 1]);
115 if(imm >= 0)
116 ccprintf(response, " + 0x%x ]", imm);
117 else
118 ccprintf(response, " + -0x%x ]", -imm);
119 if(load)
120 {
121 ccprintf(response, ", ");
122 printReg(response, _destRegIdx[0]);
123 }
124
125 return response.str();
126 }
127}};
128
129def template MemDeclare {{
130 /**
131 * Static instruction class for "%(mnemonic)s".
132 */
133 class %(class_name)s : public %(base_class)s
134 {
135 public:
136
137 /// Constructor.
138 %(class_name)s(ExtMachInst machInst);
139
140 %(BasicExecDeclare)s
141
142 %(InitiateAccDeclare)s
143
144 %(CompleteAccDeclare)s
145 };
146}};
147
148let {{
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29
30////////////////////////////////////////////////////////////////////
31//
32// Mem instructions
33//
34
35output header {{
36 /**
37 * Base class for memory operations.
38 */
39 class Mem : public SparcStaticInst
40 {
41 protected:
42
43 // Constructor
44 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
45 SparcStaticInst(mnem, _machInst, __opClass)
46 {
47 }
48
49 std::string generateDisassembly(Addr pc,
50 const SymbolTable *symtab) const;
51 };
52
53 /**
54 * Class for memory operations which use an immediate offset.
55 */
56 class MemImm : public Mem
57 {
58 protected:
59
60 // Constructor
61 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
62 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
63 {}
64
65 std::string generateDisassembly(Addr pc,
66 const SymbolTable *symtab) const;
67
68 const int32_t imm;
69 };
70}};
71
72output decoder {{
73 std::string Mem::generateDisassembly(Addr pc,
74 const SymbolTable *symtab) const
75 {
76 std::stringstream response;
77 bool load = flags[IsLoad];
78 bool save = flags[IsStore];
79
80 printMnemonic(response, mnemonic);
81 if(save)
82 {
83 printReg(response, _srcRegIdx[0]);
84 ccprintf(response, ", ");
85 }
86 ccprintf(response, "[ ");
87 printReg(response, _srcRegIdx[!save ? 0 : 1]);
88 ccprintf(response, " + ");
89 printReg(response, _srcRegIdx[!save ? 1 : 2]);
90 ccprintf(response, " ]");
91 if(load)
92 {
93 ccprintf(response, ", ");
94 printReg(response, _destRegIdx[0]);
95 }
96
97 return response.str();
98 }
99
100 std::string MemImm::generateDisassembly(Addr pc,
101 const SymbolTable *symtab) const
102 {
103 std::stringstream response;
104 bool load = flags[IsLoad];
105 bool save = flags[IsStore];
106
107 printMnemonic(response, mnemonic);
108 if(save)
109 {
110 printReg(response, _srcRegIdx[0]);
111 ccprintf(response, ", ");
112 }
113 ccprintf(response, "[ ");
114 printReg(response, _srcRegIdx[!save ? 0 : 1]);
115 if(imm >= 0)
116 ccprintf(response, " + 0x%x ]", imm);
117 else
118 ccprintf(response, " + -0x%x ]", -imm);
119 if(load)
120 {
121 ccprintf(response, ", ");
122 printReg(response, _destRegIdx[0]);
123 }
124
125 return response.str();
126 }
127}};
128
129def template MemDeclare {{
130 /**
131 * Static instruction class for "%(mnemonic)s".
132 */
133 class %(class_name)s : public %(base_class)s
134 {
135 public:
136
137 /// Constructor.
138 %(class_name)s(ExtMachInst machInst);
139
140 %(BasicExecDeclare)s
141
142 %(InitiateAccDeclare)s
143
144 %(CompleteAccDeclare)s
145 };
146}};
147
148let {{
|
149 # XXX Need to take care of pstate.hpriv as well. The lower ASIs are split
150 # into ones that are available in priv and hpriv, and those that are only
151 # available in hpriv
152 privilegedString = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
153 return new PrivilegedAction;
154 if(AsiIsAsIfUser(EXT_ASI) && !bits(Pstate,2,2))
155 return new PrivilegedAction;'''
156
157 def doMemFormat(code, execute, priv, name, Name, opt_flags):
| 149 def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
|
158 addrCalcReg = 'EA = Rs1 + Rs2;'
159 addrCalcImm = 'EA = Rs1 + imm;'
160 iop = InstObjParams(name, Name, 'Mem', code,
| 150 addrCalcReg = 'EA = Rs1 + Rs2;'
151 addrCalcImm = 'EA = Rs1 + imm;'
152 iop = InstObjParams(name, Name, 'Mem', code,
|
161 opt_flags, {"priv_check": priv, "ea_code": addrCalcReg})
| 153 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcReg})
|
162 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code,
| 154 iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code,
|
163 opt_flags, {"priv_check": priv, "ea_code": addrCalcImm})
| 155 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcImm})
|
164 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
165 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
166 decode_block = ROrImmDecode.subst(iop)
167 exec_output = doSplitExecute(code, addrCalcReg, addrCalcImm, execute,
| 156 header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
157 decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
158 decode_block = ROrImmDecode.subst(iop)
159 exec_output = doSplitExecute(code, addrCalcReg, addrCalcImm, execute,
|
168 priv, name, name + "Imm", Name, Name + "Imm", opt_flags)
| 160 faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags)
|
169 return (header_output, decoder_output, exec_output, decode_block)
170}};
171
172def format LoadAlt(code, *opt_flags) {{
173 (header_output,
174 decoder_output,
175 exec_output,
176 decode_block) = doMemFormat(code, LoadExecute,
| 161 return (header_output, decoder_output, exec_output, decode_block)
162}};
163
164def format LoadAlt(code, *opt_flags) {{
165 (header_output,
166 decoder_output,
167 exec_output,
168 decode_block) = doMemFormat(code, LoadExecute,
|
177 privelegedString, name, Name, opt_flags)
| 169 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
|
178}};
179
180def format StoreAlt(code, *opt_flags) {{
181 (header_output,
182 decoder_output,
183 exec_output,
184 decode_block) = doMemFormat(code, StoreExecute,
| 170}};
171
172def format StoreAlt(code, *opt_flags) {{
173 (header_output,
174 decoder_output,
175 exec_output,
176 decode_block) = doMemFormat(code, StoreExecute,
|
185 privilegedString, name, Name, opt_flags)
| 177 AlternateAsiPrivFaultCheck, name, Name, opt_flags)
|
186}};
187
188def format Load(code, *opt_flags) {{
189 (header_output,
190 decoder_output,
191 exec_output,
192 decode_block) = doMemFormat(code,
193 LoadExecute, '', name, Name, opt_flags)
194}};
195
196def format Store(code, *opt_flags) {{
197 (header_output,
198 decoder_output,
199 exec_output,
200 decode_block) = doMemFormat(code,
201 StoreExecute, '', name, Name, opt_flags)
202}};
| 178}};
179
180def format Load(code, *opt_flags) {{
181 (header_output,
182 decoder_output,
183 exec_output,
184 decode_block) = doMemFormat(code,
185 LoadExecute, '', name, Name, opt_flags)
186}};
187
188def format Store(code, *opt_flags) {{
189 (header_output,
190 decoder_output,
191 exec_output,
192 decode_block) = doMemFormat(code,
193 StoreExecute, '', name, Name, opt_flags)
194}};
|