integerop.isa (2646:c5f20661d9f3) integerop.isa (2944:10dcffb2904f)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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127 class SetHi : public IntOpImm
128 {
129 protected:
130 // Constructor
131 SetHi(const char *mnem, ExtMachInst _machInst,
132 OpClass __opClass) :
133 IntOpImm(mnem, _machInst, __opClass)
134 {
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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127 class SetHi : public IntOpImm
128 {
129 protected:
130 // Constructor
131 SetHi(const char *mnem, ExtMachInst _machInst,
132 OpClass __opClass) :
133 IntOpImm(mnem, _machInst, __opClass)
134 {
135 imm = (IMM22 << 10) & 0xFFFFFC00;
135 imm = (IMM22 & 0x3FFFFF) << 10;
136 }
137
138 std::string generateDisassembly(Addr pc,
139 const SymbolTable *symtab) const;
140 };
141}};
142
143def template SetHiDecode {{

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152output decoder {{
153
154 bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
155 const SymbolTable *symbab) const
156 {
157 if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
158 {
159 printMnemonic(os, "mov");
136 }
137
138 std::string generateDisassembly(Addr pc,
139 const SymbolTable *symtab) const;
140 };
141}};
142
143def template SetHiDecode {{

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152output decoder {{
153
154 bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
155 const SymbolTable *symbab) const
156 {
157 if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
158 {
159 printMnemonic(os, "mov");
160 if(_numSrcRegs > 0)
161 printReg(os, _srcRegIdx[1]);
160 printSrcReg(os, 1);
162 ccprintf(os, ", ");
161 ccprintf(os, ", ");
163 if(_numDestRegs > 0)
164 printReg(os, _destRegIdx[0]);
165
162 printDestReg(os, 0);
166 return true;
167 }
168 return false;
169 }
170
171 bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
172 const SymbolTable *symbab) const
173 {
174 if(!strcmp(mnemonic, "or"))
175 {
163 return true;
164 }
165 return false;
166 }
167
168 bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
169 const SymbolTable *symbab) const
170 {
171 if(!strcmp(mnemonic, "or"))
172 {
176 if(_srcRegIdx[0] == 0)
173 if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
177 {
178 if(imm == 0)
174 {
175 if(imm == 0)
179 {
180 printMnemonic(os, "clr");
176 printMnemonic(os, "clr");
181 if(_numDestRegs > 0)
182 printReg(os, _destRegIdx[0]);
183 return true;
184 }
185 else
186 {
187 printMnemonic(os, "mov");
177 else
178 {
179 printMnemonic(os, "mov");
188 ccprintf(os, ", 0x%x, ", imm);
189 if(_numDestRegs > 0)
190 printReg(os, _destRegIdx[0]);
191 return true;
180 ccprintf(os, " 0x%x, ", imm);
192 }
181 }
182 printDestReg(os, 0);
183 return true;
193 }
194 else if(imm == 0)
195 {
196 printMnemonic(os, "mov");
184 }
185 else if(imm == 0)
186 {
187 printMnemonic(os, "mov");
197 if(_numSrcRegs > 0)
198 printReg(os, _srcRegIdx[0]);
188 printSrcReg(os, 0);
199 ccprintf(os, ", ");
189 ccprintf(os, ", ");
200 if(_numDestRegs > 0)
201 printReg(os, _destRegIdx[0]);
190 printDestReg(os, 0);
202 return true;
203 }
204 }
205 return false;
206 }
207
208 std::string IntOp::generateDisassembly(Addr pc,
209 const SymbolTable *symtab) const
210 {
211 std::stringstream response;
212
191 return true;
192 }
193 }
194 return false;
195 }
196
197 std::string IntOp::generateDisassembly(Addr pc,
198 const SymbolTable *symtab) const
199 {
200 std::stringstream response;
201
213 if(!printPseudoOps(response, pc, symtab))
214 {
215 printMnemonic(response, mnemonic);
216 if (_numSrcRegs > 0)
217 {
218 printReg(response, _srcRegIdx[0]);
219 for(int x = 1; x < _numSrcRegs; x++)
220 {
221 response << ", ";
222 printReg(response, _srcRegIdx[x]);
223 }
224 }
225 if (_numDestRegs > 0)
226 {
227 if(_numSrcRegs > 0)
228 response << ", ";
229 printReg(response, _destRegIdx[0]);
230 }
231 }
202 if(printPseudoOps(response, pc, symtab))
203 return response.str();
204 printMnemonic(response, mnemonic);
205 printRegArray(response, _srcRegIdx, _numSrcRegs);
206 if(_numDestRegs && _numSrcRegs)
207 response << ", ";
208 printDestReg(response, 0);
232 return response.str();
233 }
234
235 std::string IntOpImm::generateDisassembly(Addr pc,
236 const SymbolTable *symtab) const
237 {
238 std::stringstream response;
239
209 return response.str();
210 }
211
212 std::string IntOpImm::generateDisassembly(Addr pc,
213 const SymbolTable *symtab) const
214 {
215 std::stringstream response;
216
240 if(!printPseudoOps(response, pc, symtab))
241 {
242 printMnemonic(response, mnemonic);
243 if (_numSrcRegs > 0)
244 {
245 printReg(response, _srcRegIdx[0]);
246 for(int x = 1; x < _numSrcRegs - 1; x++)
247 {
248 response << ", ";
249 printReg(response, _srcRegIdx[x]);
250 }
251 }
252 if(_numSrcRegs > 0)
253 response << ", ";
254 ccprintf(response, "0x%x", imm);
255 if (_numDestRegs > 0)
256 {
257 response << ", ";
258 printReg(response, _destRegIdx[0]);
259 }
260 }
217 if(printPseudoOps(response, pc, symtab))
218 return response.str();
219 printMnemonic(response, mnemonic);
220 printRegArray(response, _srcRegIdx, _numSrcRegs);
221 if(_numSrcRegs > 0)
222 response << ", ";
223 ccprintf(response, "0x%x", imm);
224 if(_numDestRegs > 0)
225 response << ", ";
226 printDestReg(response, 0);
261 return response.str();
262 }
263
264 std::string SetHi::generateDisassembly(Addr pc,
265 const SymbolTable *symtab) const
266 {
267 std::stringstream response;
268
269 printMnemonic(response, mnemonic);
227 return response.str();
228 }
229
230 std::string SetHi::generateDisassembly(Addr pc,
231 const SymbolTable *symtab) const
232 {
233 std::stringstream response;
234
235 printMnemonic(response, mnemonic);
270 if(_numSrcRegs > 0)
271 response << ", ";
272 ccprintf(response, "%%hi(0x%x), ", imm);
236 ccprintf(response, "%%hi(0x%x), ", imm);
273 printReg(response, _destRegIdx[0]);
237 printDestReg(response, 0);
274 return response.str();
275 }
276}};
277
278def template IntOpExecute {{
279 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
280 Trace::InstRecord *traceData) const
281 {

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311 decoder_output += BasicConstructor.subst(imm_iop)
312 exec_output += IntOpExecute.subst(imm_iop)
313 decode_block = ROrImmDecode.subst(iop)
314 else:
315 decode_block = BasicDecode.subst(iop)
316 return (header_output, decoder_output, exec_output, decode_block)
317
318 calcCcCode = '''
238 return response.str();
239 }
240}};
241
242def template IntOpExecute {{
243 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
244 Trace::InstRecord *traceData) const
245 {

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275 decoder_output += BasicConstructor.subst(imm_iop)
276 exec_output += IntOpExecute.subst(imm_iop)
277 decode_block = ROrImmDecode.subst(iop)
278 else:
279 decode_block = BasicDecode.subst(iop)
280 return (header_output, decoder_output, exec_output, decode_block)
281
282 calcCcCode = '''
319 uint8_t tmp_ccriccc;
320 uint8_t tmp_ccriccv;
321 uint8_t tmp_ccriccz;
322 uint8_t tmp_ccriccn;
323 uint8_t tmp_ccrxccc;
324 uint8_t tmp_ccrxccv;
325 uint8_t tmp_ccrxccz;
326 uint8_t tmp_ccrxccn;
283 uint16_t _ic, _iv, _iz, _in, _xc, _xv, _xz, _xn;
327
284
328 tmp_ccriccn = (Rd >> 31) & 1;
329 tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0);
330 tmp_ccrxccn = (Rd >> 63) & 1;
331 tmp_ccrxccz = (Rd == 0);
332 tmp_ccriccv = %(ivValue)s & 1;
333 tmp_ccriccc = %(icValue)s & 1;
334 tmp_ccrxccv = %(xvValue)s & 1;
335 tmp_ccrxccc = %(xcValue)s & 1;
285 _in = (Rd >> 31) & 1;
286 _iz = ((Rd & 0xFFFFFFFF) == 0);
287 _xn = (Rd >> 63) & 1;
288 _xz = (Rd == 0);
289 _iv = %(ivValue)s & 1;
290 _ic = %(icValue)s & 1;
291 _xv = %(xvValue)s & 1;
292 _xc = %(xcValue)s & 1;
336
293
337 Ccr = tmp_ccriccc | tmp_ccriccv << 1 |
338 tmp_ccriccz << 2 | tmp_ccriccn << 3|
339 tmp_ccrxccc << 4 | tmp_ccrxccv << 5|
340 tmp_ccrxccz << 6| tmp_ccrxccn << 7;
294 Ccr = _ic << 0 | _iv << 1 | _iz << 2 | _in << 3 |
295 _xc << 4 | _xv << 5 | _xz << 6 | _xn << 7;
341
342
296
297
343 DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn);
344 DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz);
345 DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn);
346 DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz);
347 DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv);
348 DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc);
349 DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv);
350 DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc);
298 DPRINTF(Sparc, "in = %%d\\n", _in);
299 DPRINTF(Sparc, "iz = %%d\\n", _iz);
300 DPRINTF(Sparc, "xn = %%d\\n", _xn);
301 DPRINTF(Sparc, "xz = %%d\\n", _xz);
302 DPRINTF(Sparc, "iv = %%d\\n", _iv);
303 DPRINTF(Sparc, "ic = %%d\\n", _ic);
304 DPRINTF(Sparc, "xv = %%d\\n", _xv);
305 DPRINTF(Sparc, "xc = %%d\\n", _xc);
351 '''
352}};
353
354// Primary format for integer operate instructions:
355def format IntOp(code, *opt_flags) {{
356 ccCode = ''
357 (header_output,
358 decoder_output,

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307}};
308
309// Primary format for integer operate instructions:
310def format IntOp(code, *opt_flags) {{
311 ccCode = ''
312 (header_output,
313 decoder_output,

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