145c145
< if(RD == 0 && IMM22 == 0)
---
> if (RD == 0 && IMM22 == 0)
154c154,155
< bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
---
> bool
> IntOp::printPseudoOps(std::ostream &os, Addr pc,
157,158c158
< if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
< {
---
> if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
168c168,169
< bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
---
> bool
> IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
171,175c172,174
< if(!std::strcmp(mnemonic, "or"))
< {
< if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
< {
< if(imm == 0)
---
> if (!std::strcmp(mnemonic, "or")) {
> if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
> if (imm == 0) {
177,178c176
< else
< {
---
> } else {
184,186c182
< }
< else if(imm == 0)
< {
---
> } else if (imm == 0) {
197,198c193,194
< std::string IntOp::generateDisassembly(Addr pc,
< const SymbolTable *symtab) const
---
> std::string
> IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
202c198
< if(printPseudoOps(response, pc, symtab))
---
> if (printPseudoOps(response, pc, symtab))
206c202
< if(_numDestRegs && _numSrcRegs)
---
> if (_numDestRegs && _numSrcRegs)
212c208,209
< std::string IntOpImm::generateDisassembly(Addr pc,
---
> std::string
> IntOpImm::generateDisassembly(Addr pc,
217c214
< if(printPseudoOps(response, pc, symtab))
---
> if (printPseudoOps(response, pc, symtab))
221c218
< if(_numSrcRegs > 0)
---
> if (_numSrcRegs > 0)
224c221
< if(_numDestRegs > 0)
---
> if (_numDestRegs > 0)
230,231c227,228
< std::string SetHi::generateDisassembly(Addr pc,
< const SymbolTable *symtab) const
---
> std::string
> SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const
252,254c249,250
< //Write the resulting state to the execution context
< if(fault == NoFault)
< {
---
> // Write the resulting state to the execution context
> if (fault == NoFault) {