| branch.isa (7741:340b6f01d69b) | branch.isa (7790:9df469679ac7) |
|---|---|
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 181 unchanged lines hidden (view full) --- 190 Trace::InstRecord *traceData) const 191 { 192 // Attempt to execute the instruction 193 Fault fault = NoFault; 194 195 %(op_decl)s; 196 %(op_rd)s; 197 | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 181 unchanged lines hidden (view full) --- 190 Trace::InstRecord *traceData) const 191 { 192 // Attempt to execute the instruction 193 Fault fault = NoFault; 194 195 %(op_decl)s; 196 %(op_rd)s; 197 |
| 198 PCS = PCS; | |
| 199 %(code)s; 200 201 if (fault == NoFault) { 202 // Write the resulting state to the execution context 203 %(op_wb)s; 204 } 205 206 return fault; --- 30 unchanged lines hidden (view full) --- 237 if (A) 238 return new %(class_name)sAnnul("%(mnemonic)s,a", machInst); 239 else 240 return new %(class_name)s("%(mnemonic)s", machInst); 241}}; 242 243// Primary format for branch instructions: 244def format Branch(code, *opt_flags) {{ | 198 %(code)s; 199 200 if (fault == NoFault) { 201 // Write the resulting state to the execution context 202 %(op_wb)s; 203 } 204 205 return fault; --- 30 unchanged lines hidden (view full) --- 236 if (A) 237 return new %(class_name)sAnnul("%(mnemonic)s,a", machInst); 238 else 239 return new %(class_name)s("%(mnemonic)s", machInst); 240}}; 241 242// Primary format for branch instructions: 243def format Branch(code, *opt_flags) {{ |
| 244 code = 'NNPC = NNPC;\n' + code |
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| 245 (usesImm, code, immCode, 246 rString, iString) = splitOutImm(code) 247 iop = InstObjParams(name, Name, 'Branch', code, opt_flags) 248 header_output = BasicDeclare.subst(iop) 249 decoder_output = BasicConstructor.subst(iop) 250 exec_output = JumpExecute.subst(iop) 251 if usesImm: 252 imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, --- 32 unchanged lines hidden (view full) --- 285 opt_flags) 286 header_output += BasicDeclareWithMnemonic.subst(iop) 287 decoder_output += BasicConstructorWithMnemonic.subst(iop) 288 exec_output += BranchExecute.subst(iop) 289 return (header_output, decoder_output, exec_output, decode_block) 290 291 def doCondBranch(name, Name, base, cond, code, opt_flags): 292 return doBranch(name, Name, base, cond, code, code, | 245 (usesImm, code, immCode, 246 rString, iString) = splitOutImm(code) 247 iop = InstObjParams(name, Name, 'Branch', code, opt_flags) 248 header_output = BasicDeclare.subst(iop) 249 decoder_output = BasicConstructor.subst(iop) 250 exec_output = JumpExecute.subst(iop) 251 if usesImm: 252 imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, --- 32 unchanged lines hidden (view full) --- 285 opt_flags) 286 header_output += BasicDeclareWithMnemonic.subst(iop) 287 decoder_output += BasicConstructorWithMnemonic.subst(iop) 288 exec_output += BranchExecute.subst(iop) 289 return (header_output, decoder_output, exec_output, decode_block) 290 291 def doCondBranch(name, Name, base, cond, code, opt_flags): 292 return doBranch(name, Name, base, cond, code, code, |
| 293 'PCS = PCS;', 294 ''' 295 SparcISA::PCState pc = PCS; 296 pc.nnpc(pc.npc() + 8); 297 pc.npc(pc.npc() + 4); 298 PCS = pc; 299 ''', | 293 'NNPC = NNPC; NPC = NPC;\n', 294 'NNPC = NPC + 8; NPC = NPC + 4;\n', |
| 300 opt_flags) 301 302 def doUncondBranch(name, Name, base, code, annul_code, opt_flags): 303 return doBranch(name, Name, base, "true", code, annul_code, 304 ";", ";", opt_flags) 305 | 295 opt_flags) 296 297 def doUncondBranch(name, Name, base, code, annul_code, opt_flags): 298 return doBranch(name, Name, base, "true", code, annul_code, 299 ";", ";", opt_flags) 300 |
| 306 default_branch_code = ''' 307 SparcISA::PCState pc = PCS; 308 pc.nnpc(pc.pc() + disp); 309 PCS = pc; 310 ''' | 301 default_branch_code = 'NNPC = PC + disp;\n' |
| 311}}; 312 313// Format for branch instructions with n bit displacements: 314def format BranchN(bits, code=default_branch_code, 315 test=None, annul_code=None, *opt_flags) {{ 316 if code == "default_branch_code": 317 code = default_branch_code 318 if test != "None": --- 32 unchanged lines hidden --- | 302}}; 303 304// Format for branch instructions with n bit displacements: 305def format BranchN(bits, code=default_branch_code, 306 test=None, annul_code=None, *opt_flags) {{ 307 if code == "default_branch_code": 308 code = default_branch_code 309 if test != "None": --- 32 unchanged lines hidden --- |