branch.isa (5091:662c1d7b4795) branch.isa (7720:65d338a8dba4)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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188 Trace::InstRecord *traceData) const
189 {
190 //Attempt to execute the instruction
191 Fault fault = NoFault;
192
193 %(op_decl)s;
194 %(op_rd)s;
195
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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188 Trace::InstRecord *traceData) const
189 {
190 //Attempt to execute the instruction
191 Fault fault = NoFault;
192
193 %(op_decl)s;
194 %(op_rd)s;
195
196 NNPC = xc->readNextNPC();
196 PCS = PCS;
197 %(code)s;
198
199 if(fault == NoFault)
200 {
201 //Write the resulting state to the execution context
202 %(op_wb)s;
203 }
204

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284 opt_flags)
285 header_output += BasicDeclareWithMnemonic.subst(iop)
286 decoder_output += BasicConstructorWithMnemonic.subst(iop)
287 exec_output += BranchExecute.subst(iop)
288 return (header_output, decoder_output, exec_output, decode_block)
289
290 def doCondBranch(name, Name, base, cond, code, opt_flags):
291 return doBranch(name, Name, base, cond, code, code,
197 %(code)s;
198
199 if(fault == NoFault)
200 {
201 //Write the resulting state to the execution context
202 %(op_wb)s;
203 }
204

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284 opt_flags)
285 header_output += BasicDeclareWithMnemonic.subst(iop)
286 decoder_output += BasicConstructorWithMnemonic.subst(iop)
287 exec_output += BranchExecute.subst(iop)
288 return (header_output, decoder_output, exec_output, decode_block)
289
290 def doCondBranch(name, Name, base, cond, code, opt_flags):
291 return doBranch(name, Name, base, cond, code, code,
292 'NPC = NPC; NNPC = NNPC;',
293 'NNPC = NPC + 8; NPC = NPC + 4',
292 'PCS = PCS;',
293 '''
294 SparcISA::PCState pc = PCS;
295 pc.nnpc(pc.npc() + 8);
296 pc.npc(pc.npc() + 4);
297 PCS = pc;
298 ''',
294 opt_flags)
295
296 def doUncondBranch(name, Name, base, code, annul_code, opt_flags):
297 return doBranch(name, Name, base, "true", code, annul_code,
298 ";", ";", opt_flags)
299
299 opt_flags)
300
301 def doUncondBranch(name, Name, base, code, annul_code, opt_flags):
302 return doBranch(name, Name, base, "true", code, annul_code,
303 ";", ";", opt_flags)
304
300 default_branch_code = "NNPC = xc->readPC() + disp;"
305 default_branch_code = '''
306 SparcISA::PCState pc = PCS;
307 pc.nnpc(pc.pc() + disp);
308 PCS = pc;
309 '''
301}};
302
303// Format for branch instructions with n bit displacements:
304def format BranchN(bits, code=default_branch_code,
305 test=None, annul_code=None, *opt_flags) {{
306 if code == "default_branch_code":
307 code = default_branch_code
308 if test != "None":

--- 32 unchanged lines hidden --- 		310}};
311
312// Format for branch instructions with n bit displacements:
313def format BranchN(bits, code=default_branch_code,
314 test=None, annul_code=None, *opt_flags) {{
315 if code == "default_branch_code":
316 code = default_branch_code
317 if test != "None":

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