1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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64
65 std::string generateDisassembly(Addr pc,
66 const SymbolTable *symtab) const;
67
68 int32_t disp;
69 };
70
71 /**
72 * Base class for branches with n bit displacements.
73 */
74 template<int bits>
75 class BranchNBits : public BranchDisp
76 {
77 protected:
78 // Constructor
79 BranchNBits(const char *mnem, MachInst _machInst,
80 OpClass __opClass) :
81 BranchDisp(mnem, _machInst, __opClass)
82 {
83 disp = sign_ext(_machInst << 2, bits + 2);
84 }
85 };
86
87 /**
88 * Base class for 16bit split displacements.
89 */
90 class BranchSplit : public BranchDisp
91 {
92 protected:
93 // Constructor
94 BranchSplit(const char *mnem, MachInst _machInst,
95 OpClass __opClass) :

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115 std::string generateDisassembly(Addr pc,
116 const SymbolTable *symtab) const;
117
118 int32_t imm;
119 };
120}};
121
122output decoder {{
123
124 template class BranchNBits<19>;
125
126 template class BranchNBits<22>;
127
128 template class BranchNBits<30>;
129
130 std::string Branch::generateDisassembly(Addr pc,
131 const SymbolTable *symtab) const
132 {
133 std::stringstream response;
134
135 printMnemonic(response, mnemonic);
136 printRegArray(response, _srcRegIdx, _numSrcRegs);
137 if(_numDestRegs && _numSrcRegs)
138 response << ", ";
139 printDestReg(response, 0);
140
141 return response.str();
142 }
143
144 std::string BranchImm13::generateDisassembly(Addr pc,
145 const SymbolTable *symtab) const
146 {
147 std::stringstream response;
148
149 printMnemonic(response, mnemonic);
150 printRegArray(response, _srcRegIdx, _numSrcRegs);
151 if(_numSrcRegs > 0)
152 response << ", ";
153 ccprintf(response, "0x%x", imm);
154 if (_numDestRegs > 0)
155 response << ", ";
156 printDestReg(response, 0);
157
158 return response.str();
159 }
160
161 std::string BranchDisp::generateDisassembly(Addr pc,
162 const SymbolTable *symtab) const
163 {
164 std::stringstream response;

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238 decoder_output += BasicConstructor.subst(imm_iop)
239 exec_output += BranchExecute.subst(imm_iop)
240 decode_block = ROrImmDecode.subst(iop)
241 else:
242 decode_block = BasicDecode.subst(iop)
243}};
244
245// Primary format for branch instructions:
246def format BranchN(bits, code, *opt_flags) {{
247 code = re.sub(r'handle_annul', handle_annul, code)
248 codeBlk = CodeBlock(code)
249 iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags)
250 header_output = BasicDeclare.subst(iop)
251 decoder_output = BasicConstructor.subst(iop)
252 exec_output = BranchExecute.subst(iop)
253 decode_block = BasicDecode.subst(iop)
254}};
255
256// Primary format for branch instructions:
257def format BranchSplit(code, *opt_flags) {{
258 code = re.sub(r'handle_annul', handle_annul, code)
259 codeBlk = CodeBlock(code)
260 iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
261 header_output = BasicDeclare.subst(iop)
262 decoder_output = BasicConstructor.subst(iop)
263 exec_output = BranchExecute.subst(iop)
264 decode_block = BasicDecode.subst(iop)
265}};
266