decoder.isa (8556:2afd82e84d95) | decoder.isa (8588:ef28ed90449d) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 68 unchanged lines hidden (view full) --- 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 68 unchanged lines hidden (view full) --- 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { |
85 0x1: bpreq(test={{Rs1.sdw == 0}}); 86 0x2: bprle(test={{Rs1.sdw <= 0}}); 87 0x3: bprl(test={{Rs1.sdw < 0}}); 88 0x5: bprne(test={{Rs1.sdw != 0}}); 89 0x6: bprg(test={{Rs1.sdw > 0}}); 90 0x7: bprge(test={{Rs1.sdw >= 0}}); | 85 0x1: bpreq(test={{Rs1_sdw == 0}}); 86 0x2: bprle(test={{Rs1_sdw <= 0}}); 87 0x3: bprl(test={{Rs1_sdw < 0}}); 88 0x5: bprne(test={{Rs1_sdw != 0}}); 89 0x6: bprg(test={{Rs1_sdw > 0}}); 90 0x7: bprge(test={{Rs1_sdw >= 0}}); |
91 } 92 } 93 // SETHI (or NOP if rd == 0 and imm == 0) | 91 } 92 } 93 // SETHI (or NOP if rd == 0 and imm == 0) |
94 0x4: SetHi::sethi({{Rd.udw = imm;}}); | 94 0x4: SetHi::sethi({{Rd_udw = imm;}}); |
95 // fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 // Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = PC + disp; 101 NNPC = PC + disp + 4; 102 }}); --- 36 unchanged lines hidden (view full) --- 139 } 140 0x1: BranchN::call(30, {{ 141 IntReg midVal; 142 R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC); 143 NNPC = midVal + disp; 144 }},None, None, IsIndirectControl, IsCall); 145 0x2: decode OP3 { 146 format IntOp { | 95 // fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 // Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = PC + disp; 101 NNPC = PC + disp + 4; 102 }}); --- 36 unchanged lines hidden (view full) --- 139 } 140 0x1: BranchN::call(30, {{ 141 IntReg midVal; 142 R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC); 143 NNPC = midVal + disp; 144 }},None, None, IsIndirectControl, IsCall); 145 0x2: decode OP3 { 146 format IntOp { |
147 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 148 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 149 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 150 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 151 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 152 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 153 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 154 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 155 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 156 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); | 147 0x00: add({{Rd = Rs1_sdw + Rs2_or_imm13;}}); 148 0x01: and({{Rd = Rs1_sdw & Rs2_or_imm13;}}); 149 0x02: or({{Rd = Rs1_sdw | Rs2_or_imm13;}}); 150 0x03: xor({{Rd = Rs1_sdw ^ Rs2_or_imm13;}}); 151 0x04: sub({{Rd = Rs1_sdw - Rs2_or_imm13;}}); 152 0x05: andn({{Rd = Rs1_sdw & ~Rs2_or_imm13;}}); 153 0x06: orn({{Rd = Rs1_sdw | ~Rs2_or_imm13;}}); 154 0x07: xnor({{Rd = ~(Rs1_sdw ^ Rs2_or_imm13);}}); 155 0x08: addc({{Rd = Rs1_sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 156 0x09: mulx({{Rd = Rs1_sdw * Rs2_or_imm13;}}); |
157 0x0A: umul({{ | 157 0x0A: umul({{ |
158 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; | 158 Rd = Rs1_udw<31:0> * Rs2_or_imm13<31:0>; |
159 Y = Rd<63:32>; 160 }}); 161 0x0B: smul({{ | 159 Y = Rd<63:32>; 160 }}); 161 0x0B: smul({{ |
162 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 163 Y = Rd.sdw<63:32>; | 162 Rd_sdw = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 163 Y = Rd_sdw<63:32>; |
164 }}); | 164 }}); |
165 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); | 165 0x0C: subc({{Rd_sdw = Rs1_sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); |
166 0x0D: udivx({{ 167 if (Rs2_or_imm13 == 0) 168 fault = new DivisionByZero; 169 else | 166 0x0D: udivx({{ 167 if (Rs2_or_imm13 == 0) 168 fault = new DivisionByZero; 169 else |
170 Rd.udw = Rs1.udw / Rs2_or_imm13; | 170 Rd_udw = Rs1_udw / Rs2_or_imm13; |
171 }}); 172 0x0E: udiv({{ 173 if (Rs2_or_imm13 == 0) { 174 fault = new DivisionByZero; 175 } else { | 171 }}); 172 0x0E: udiv({{ 173 if (Rs2_or_imm13 == 0) { 174 fault = new DivisionByZero; 175 } else { |
176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 177 if (Rd.udw >> 32 != 0) 178 Rd.udw = 0xFFFFFFFF; | 176 Rd_udw = ((Y << 32) | Rs1_udw<31:0>) / Rs2_or_imm13; 177 if (Rd_udw >> 32 != 0) 178 Rd_udw = 0xFFFFFFFF; |
179 } 180 }}); 181 0x0F: sdiv({{ | 179 } 180 }}); 181 0x0F: sdiv({{ |
182 if (Rs2_or_imm13.sdw == 0) { | 182 if (Rs2_or_imm13_sdw == 0) { |
183 fault = new DivisionByZero; 184 } else { | 183 fault = new DivisionByZero; 184 } else { |
185 Rd.udw = ((int64_t)((Y << 32) | 186 Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 187 if ((int64_t)Rd.udw >= | 185 Rd_udw = ((int64_t)((Y << 32) | 186 Rs1_sdw<31:0>)) / Rs2_or_imm13_sdw; 187 if ((int64_t)Rd_udw >= |
188 std::numeric_limits<int32_t>::max()) { | 188 std::numeric_limits<int32_t>::max()) { |
189 Rd.udw = 0x7FFFFFFF; 190 } else if ((int64_t)Rd.udw <= | 189 Rd_udw = 0x7FFFFFFF; 190 } else if ((int64_t)Rd_udw <= |
191 std::numeric_limits<int32_t>::min()) { | 191 std::numeric_limits<int32_t>::min()) { |
192 Rd.udw = ULL(0xFFFFFFFF80000000); | 192 Rd_udw = ULL(0xFFFFFFFF80000000); |
193 } 194 } 195 }}); 196 } 197 format IntOpCc { 198 0x10: addcc({{ 199 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 200 Rd = res = op1 + op2; --- 9 unchanged lines hidden (view full) --- 210 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 211 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 212 0x18: addccc({{ 213 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 214 Rd = res = op1 + op2 + Ccr<0:>; 215 }}); 216 0x1A: IntOpCcRes::umulcc({{ 217 uint64_t resTemp; | 193 } 194 } 195 }}); 196 } 197 format IntOpCc { 198 0x10: addcc({{ 199 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 200 Rd = res = op1 + op2; --- 9 unchanged lines hidden (view full) --- 210 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 211 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 212 0x18: addccc({{ 213 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 214 Rd = res = op1 + op2 + Ccr<0:>; 215 }}); 216 0x1A: IntOpCcRes::umulcc({{ 217 uint64_t resTemp; |
218 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; | 218 Rd = resTemp = Rs1_udw<31:0> * Rs2_or_imm13_udw<31:0>; |
219 Y = resTemp<63:32>;}}); 220 0x1B: IntOpCcRes::smulcc({{ 221 int64_t resTemp; | 219 Y = resTemp<63:32>;}}); 220 0x1B: IntOpCcRes::smulcc({{ 221 int64_t resTemp; |
222 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); | 222 Rd = resTemp = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); |
223 Y = resTemp<63:32>;}}); 224 0x1C: subccc({{ 225 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 226 Rd = res = op1 - op2 - Ccr<0:>; 227 }}, sub=True); 228 0x1D: IntOpCcRes::udivxcc({{ | 223 Y = resTemp<63:32>;}}); 224 0x1C: subccc({{ 225 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 226 Rd = res = op1 - op2 - Ccr<0:>; 227 }}, sub=True); 228 0x1D: IntOpCcRes::udivxcc({{ |
229 if (Rs2_or_imm13.udw == 0) | 229 if (Rs2_or_imm13_udw == 0) |
230 fault = new DivisionByZero; 231 else | 230 fault = new DivisionByZero; 231 else |
232 Rd = Rs1.udw / Rs2_or_imm13.udw;}}); | 232 Rd = Rs1_udw / Rs2_or_imm13_udw;}}); |
233 0x1E: IntOpCcRes::udivcc({{ 234 uint64_t resTemp; | 233 0x1E: IntOpCcRes::udivcc({{ 234 uint64_t resTemp; |
235 uint32_t val2 = Rs2_or_imm13.udw; | 235 uint32_t val2 = Rs2_or_imm13_udw; |
236 int32_t overflow = 0; 237 if (val2 == 0) { 238 fault = new DivisionByZero; 239 } else { | 236 int32_t overflow = 0; 237 if (val2 == 0) { 238 fault = new DivisionByZero; 239 } else { |
240 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; | 240 resTemp = (uint64_t)((Y << 32) | Rs1_udw<31:0>) / val2; |
241 overflow = (resTemp<63:32> != 0); 242 if (overflow) 243 Rd = resTemp = 0xFFFFFFFF; 244 else 245 Rd = resTemp; 246 } 247 }}, iv={{overflow}}); 248 0x1F: IntOpCcRes::sdivcc({{ | 241 overflow = (resTemp<63:32> != 0); 242 if (overflow) 243 Rd = resTemp = 0xFFFFFFFF; 244 else 245 Rd = resTemp; 246 } 247 }}, iv={{overflow}}); 248 0x1F: IntOpCcRes::sdivcc({{ |
249 int64_t val2 = Rs2_or_imm13.sdw<31:0>; | 249 int64_t val2 = Rs2_or_imm13_sdw<31:0>; |
250 bool overflow = false, underflow = false; 251 if (val2 == 0) { 252 fault = new DivisionByZero; 253 } else { | 250 bool overflow = false, underflow = false; 251 if (val2 == 0) { 252 fault = new DivisionByZero; 253 } else { |
254 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; | 254 Rd = (int64_t)((Y << 32) | Rs1_sdw<31:0>) / val2; |
255 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 256 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 257 if (overflow) 258 Rd = 0x7FFFFFFF; 259 else if (underflow) 260 Rd = ULL(0xFFFFFFFF80000000); 261 } 262 }}, iv={{overflow || underflow}}); --- 45 unchanged lines hidden (view full) --- 308 } 309 format IntOp 310 { 311 0x25: decode X { 312 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 313 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 314 } 315 0x26: decode X { | 255 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 256 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 257 if (overflow) 258 Rd = 0x7FFFFFFF; 259 else if (underflow) 260 Rd = ULL(0xFFFFFFFF80000000); 261 } 262 }}, iv={{overflow || underflow}}); --- 45 unchanged lines hidden (view full) --- 308 } 309 format IntOp 310 { 311 0x25: decode X { 312 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 313 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 314 } 315 0x26: decode X { |
316 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 317 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); | 316 0x0: srl({{Rd = Rs1_uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 317 0x1: srlx({{Rd = Rs1_udw >> (I ? SHCNT64 : Rs2<5:0>);}}); |
318 } 319 0x27: decode X { | 318 } 319 0x27: decode X { |
320 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 321 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); | 320 0x0: sra({{Rd = Rs1_sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 321 0x1: srax({{Rd = Rs1_sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); |
322 } 323 0x28: decode RS1 { 324 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 325 // 1 should cause an illegal instruction exception 326 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 327 0x03: NoPriv::rdasi({{Rd = Asi;}}); 328 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 329 0x05: NoPriv::rdpc({{ --- 115 unchanged lines hidden (view full) --- 445 if (passesCondition(Ccr<7:4>, COND4)) 446 Rd = Rs2_or_imm11; 447 else 448 Rd = Rd; 449 }}); 450 } 451 } 452 0x2D: sdivx({{ | 322 } 323 0x28: decode RS1 { 324 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 325 // 1 should cause an illegal instruction exception 326 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 327 0x03: NoPriv::rdasi({{Rd = Asi;}}); 328 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 329 0x05: NoPriv::rdpc({{ --- 115 unchanged lines hidden (view full) --- 445 if (passesCondition(Ccr<7:4>, COND4)) 446 Rd = Rs2_or_imm11; 447 else 448 Rd = Rd; 449 }}); 450 } 451 } 452 0x2D: sdivx({{ |
453 if (Rs2_or_imm13.sdw == 0) | 453 if (Rs2_or_imm13_sdw == 0) |
454 fault = new DivisionByZero; 455 else | 454 fault = new DivisionByZero; 455 else |
456 Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; | 456 Rd_sdw = Rs1_sdw / Rs2_or_imm13_sdw; |
457 }}); 458 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 459 0x2F: decode RCOND3 460 { | 457 }}); 458 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 459 0x2F: decode RCOND3 460 { |
461 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 462 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 463 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 464 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 465 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 466 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); | 461 0x1: movreq({{Rd = (Rs1_sdw == 0) ? Rs2_or_imm10 : Rd;}}); 462 0x2: movrle({{Rd = (Rs1_sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 463 0x3: movrl({{Rd = (Rs1_sdw < 0) ? Rs2_or_imm10 : Rd;}}); 464 0x5: movrne({{Rd = (Rs1_sdw != 0) ? Rs2_or_imm10 : Rd;}}); 465 0x6: movrg({{Rd = (Rs1_sdw > 0) ? Rs2_or_imm10 : Rd;}}); 466 0x7: movrge({{Rd = (Rs1_sdw >= 0) ? Rs2_or_imm10 : Rd;}}); |
467 } 468 0x30: decode RD { 469 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 470 // 0x01 should cause an illegal instruction exception 471 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 472 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, 473 IsSquashAfter); 474 // 0x04-0x05 should cause an illegal instruction exception --- 90 unchanged lines hidden (view full) --- 565 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 566 // 0x04 should cause an illegal instruction exception 567 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 568 // 0x06-0x01D should cause an illegal instruction exception 569 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 570 } 571 0x34: decode OPF{ 572 format FpBasic{ | 467 } 468 0x30: decode RD { 469 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 470 // 0x01 should cause an illegal instruction exception 471 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 472 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, 473 IsSquashAfter); 474 // 0x04-0x05 should cause an illegal instruction exception --- 90 unchanged lines hidden (view full) --- 565 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 566 // 0x04 should cause an illegal instruction exception 567 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 568 // 0x06-0x01D should cause an illegal instruction exception 569 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 570 } 571 0x34: decode OPF{ 572 format FpBasic{ |
573 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 574 0x02: fmovd({{Frd.udw = Frs2.udw;}}); | 573 0x01: fmovs({{Frds_uw = Frs2s_uw;}}); 574 0x02: fmovd({{Frd_udw = Frs2_udw;}}); |
575 0x03: FpUnimpl::fmovq(); | 575 0x03: FpUnimpl::fmovq(); |
576 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 577 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); | 576 0x05: fnegs({{Frds_uw = Frs2s_uw ^ (1UL << 31);}}); 577 0x06: fnegd({{Frd_udw = Frs2_udw ^ (1ULL << 63);}}); |
578 0x07: FpUnimpl::fnegq(); | 578 0x07: FpUnimpl::fnegq(); |
579 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 580 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); | 579 0x09: fabss({{Frds_uw = ((1UL << 31) - 1) & Frs2s_uw;}}); 580 0x0A: fabsd({{Frd_udw = ((1ULL << 63) - 1) & Frs2_udw;}}); |
581 0x0B: FpUnimpl::fabsq(); | 581 0x0B: FpUnimpl::fabsq(); |
582 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 583 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); | 582 0x29: fsqrts({{Frds_sf = std::sqrt(Frs2s_sf);}}); 583 0x2A: fsqrtd({{Frd_df = std::sqrt(Frs2_df);}}); |
584 0x2B: FpUnimpl::fsqrtq(); | 584 0x2B: FpUnimpl::fsqrtq(); |
585 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 586 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); | 585 0x41: fadds({{Frds_sf = Frs1s_sf + Frs2s_sf;}}); 586 0x42: faddd({{Frd_df = Frs1_df + Frs2_df;}}); |
587 0x43: FpUnimpl::faddq(); | 587 0x43: FpUnimpl::faddq(); |
588 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 589 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); | 588 0x45: fsubs({{Frds_sf = Frs1s_sf - Frs2s_sf;}}); 589 0x46: fsubd({{Frd_df = Frs1_df - Frs2_df; }}); |
590 0x47: FpUnimpl::fsubq(); | 590 0x47: FpUnimpl::fsubq(); |
591 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 592 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); | 591 0x49: fmuls({{Frds_sf = Frs1s_sf * Frs2s_sf;}}); 592 0x4A: fmuld({{Frd_df = Frs1_df * Frs2_df;}}); |
593 0x4B: FpUnimpl::fmulq(); | 593 0x4B: FpUnimpl::fmulq(); |
594 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 595 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); | 594 0x4D: fdivs({{Frds_sf = Frs1s_sf / Frs2s_sf;}}); 595 0x4E: fdivd({{Frd_df = Frs1_df / Frs2_df;}}); |
596 0x4F: FpUnimpl::fdivq(); | 596 0x4F: FpUnimpl::fdivq(); |
597 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); | 597 0x69: fsmuld({{Frd_df = Frs1s_sf * Frs2s_sf;}}); |
598 0x6E: FpUnimpl::fdmulq(); | 598 0x6E: FpUnimpl::fdmulq(); |
599 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 600 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); | 599 0x81: fstox({{Frd_sdw = static_cast<int64_t>(Frs2s_sf);}}); 600 0x82: fdtox({{Frd_sdw = static_cast<int64_t>(Frs2_df);}}); |
601 0x83: FpUnimpl::fqtox(); | 601 0x83: FpUnimpl::fqtox(); |
602 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 603 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); | 602 0x84: fxtos({{Frds_sf = static_cast<float>(Frs2_sdw);}}); 603 0x88: fxtod({{Frd_df = static_cast<double>(Frs2_sdw);}}); |
604 0x8C: FpUnimpl::fxtoq(); | 604 0x8C: FpUnimpl::fxtoq(); |
605 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 606 0xC6: fdtos({{Frds.sf = Frs2.df;}}); | 605 0xC4: fitos({{Frds_sf = static_cast<float>(Frs2s_sw);}}); 606 0xC6: fdtos({{Frds_sf = Frs2_df;}}); |
607 0xC7: FpUnimpl::fqtos(); | 607 0xC7: FpUnimpl::fqtos(); |
608 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 609 0xC9: fstod({{Frd.df = Frs2s.sf;}}); | 608 0xC8: fitod({{Frd_df = static_cast<double>(Frs2s_sw);}}); 609 0xC9: fstod({{Frd_df = Frs2s_sf;}}); |
610 0xCB: FpUnimpl::fqtod(); 611 0xCC: FpUnimpl::fitoq(); 612 0xCD: FpUnimpl::fstoq(); 613 0xCE: FpUnimpl::fdtoq(); 614 0xD1: fstoi({{ | 610 0xCB: FpUnimpl::fqtod(); 611 0xCC: FpUnimpl::fitoq(); 612 0xCD: FpUnimpl::fstoq(); 613 0xCE: FpUnimpl::fdtoq(); 614 0xD1: fstoi({{ |
615 Frds.sw = static_cast<int32_t>(Frs2s.sf); 616 float t = Frds.sw; 617 if (t != Frs2s.sf) | 615 Frds_sw = static_cast<int32_t>(Frs2s_sf); 616 float t = Frds_sw; 617 if (t != Frs2s_sf) |
618 Fsr = insertBits(Fsr, 4,0, 0x01); 619 }}); 620 0xD2: fdtoi({{ | 618 Fsr = insertBits(Fsr, 4,0, 0x01); 619 }}); 620 0xD2: fdtoi({{ |
621 Frds.sw = static_cast<int32_t>(Frs2.df); 622 double t = Frds.sw; 623 if (t != Frs2.df) | 621 Frds_sw = static_cast<int32_t>(Frs2_df); 622 double t = Frds_sw; 623 if (t != Frs2_df) |
624 Fsr = insertBits(Fsr, 4,0, 0x01); 625 }}); 626 0xD3: FpUnimpl::fqtoi(); 627 default: FailUnimpl::fpop1(); 628 } 629 } 630 0x35: decode OPF{ 631 format FpBasic{ --- 258 unchanged lines hidden (view full) --- 890 0x37: FailUnimpl::fmul8ulx16(); 891 0x38: FailUnimpl::fmuld8sux16(); 892 0x39: FailUnimpl::fmuld8ulx16(); 893 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 894 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 895 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 896 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 897 0x48: BasicOperate::faligndata({{ | 624 Fsr = insertBits(Fsr, 4,0, 0x01); 625 }}); 626 0xD3: FpUnimpl::fqtoi(); 627 default: FailUnimpl::fpop1(); 628 } 629 } 630 0x35: decode OPF{ 631 format FpBasic{ --- 258 unchanged lines hidden (view full) --- 890 0x37: FailUnimpl::fmul8ulx16(); 891 0x38: FailUnimpl::fmuld8sux16(); 892 0x39: FailUnimpl::fmuld8ulx16(); 893 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 894 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 895 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 896 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 897 0x48: BasicOperate::faligndata({{ |
898 uint64_t msbX = Frs1.udw; 899 uint64_t lsbX = Frs2.udw; | 898 uint64_t msbX = Frs1_udw; 899 uint64_t lsbX = Frs2_udw; |
900 // Some special cases need to be split out, first 901 // because they're the most likely to be used, and 902 // second because otherwise, we end up shifting by 903 // greater than the width of the type being shifted, 904 // namely 64, which produces undefined results 905 // according to the C standard. 906 switch (Gsr<2:0>) { 907 case 0: | 900 // Some special cases need to be split out, first 901 // because they're the most likely to be used, and 902 // second because otherwise, we end up shifting by 903 // greater than the width of the type being shifted, 904 // namely 64, which produces undefined results 905 // according to the C standard. 906 switch (Gsr<2:0>) { 907 case 0: |
908 Frd.udw = msbX; | 908 Frd_udw = msbX; |
909 break; 910 case 8: | 909 break; 910 case 8: |
911 Frd.udw = lsbX; | 911 Frd_udw = lsbX; |
912 break; 913 default: 914 uint64_t msbShift = Gsr<2:0> * 8; 915 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 916 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 917 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; | 912 break; 913 default: 914 uint64_t msbShift = Gsr<2:0> * 8; 915 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 916 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 917 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; |
918 Frd.udw = ((msbX & msbMask) << msbShift) | | 918 Frd_udw = ((msbX & msbMask) << msbShift) | |
919 ((lsbX & lsbMask) >> lsbShift); 920 } 921 }}); 922 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 923 0x4C: FailUnimpl::bshuffle(); 924 0x4D: FailUnimpl::fexpand(); 925 0x50: FailUnimpl::fpadd16(); 926 0x51: FailUnimpl::fpadd16s(); 927 0x52: FailUnimpl::fpadd32(); 928 0x53: FailUnimpl::fpadd32s(); 929 0x54: FailUnimpl::fpsub16(); 930 0x55: FailUnimpl::fpsub16s(); 931 0x56: FailUnimpl::fpsub32(); 932 0x57: FailUnimpl::fpsub32s(); | 919 ((lsbX & lsbMask) >> lsbShift); 920 } 921 }}); 922 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 923 0x4C: FailUnimpl::bshuffle(); 924 0x4D: FailUnimpl::fexpand(); 925 0x50: FailUnimpl::fpadd16(); 926 0x51: FailUnimpl::fpadd16s(); 927 0x52: FailUnimpl::fpadd32(); 928 0x53: FailUnimpl::fpadd32s(); 929 0x54: FailUnimpl::fpsub16(); 930 0x55: FailUnimpl::fpsub16s(); 931 0x56: FailUnimpl::fpsub32(); 932 0x57: FailUnimpl::fpsub32s(); |
933 0x60: FpBasic::fzero({{Frd.df = 0;}}); 934 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); | 933 0x60: FpBasic::fzero({{Frd_df = 0;}}); 934 0x61: FpBasic::fzeros({{Frds_sf = 0;}}); |
935 0x62: FailUnimpl::fnor(); 936 0x63: FailUnimpl::fnors(); 937 0x64: FailUnimpl::fandnot2(); 938 0x65: FailUnimpl::fandnot2s(); 939 0x66: FpBasic::fnot2({{ | 935 0x62: FailUnimpl::fnor(); 936 0x63: FailUnimpl::fnors(); 937 0x64: FailUnimpl::fandnot2(); 938 0x65: FailUnimpl::fandnot2s(); 939 0x66: FpBasic::fnot2({{ |
940 Frd.df = (double)(~((uint64_t)Frs2.df)); | 940 Frd_df = (double)(~((uint64_t)Frs2_df)); |
941 }}); 942 0x67: FpBasic::fnot2s({{ | 941 }}); 942 0x67: FpBasic::fnot2s({{ |
943 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); | 943 Frds_sf = (float)(~((uint32_t)Frs2s_sf)); |
944 }}); 945 0x68: FailUnimpl::fandnot1(); 946 0x69: FailUnimpl::fandnot1s(); 947 0x6A: FpBasic::fnot1({{ | 944 }}); 945 0x68: FailUnimpl::fandnot1(); 946 0x69: FailUnimpl::fandnot1s(); 947 0x6A: FpBasic::fnot1({{ |
948 Frd.df = (double)(~((uint64_t)Frs1.df)); | 948 Frd_df = (double)(~((uint64_t)Frs1_df)); |
949 }}); 950 0x6B: FpBasic::fnot1s({{ | 949 }}); 950 0x6B: FpBasic::fnot1s({{ |
951 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); | 951 Frds_sf = (float)(~((uint32_t)Frs1s_sf)); |
952 }}); 953 0x6C: FailUnimpl::fxor(); 954 0x6D: FailUnimpl::fxors(); 955 0x6E: FailUnimpl::fnand(); 956 0x6F: FailUnimpl::fnands(); 957 0x70: FailUnimpl::fand(); 958 0x71: FailUnimpl::fands(); 959 0x72: FailUnimpl::fxnor(); 960 0x73: FailUnimpl::fxnors(); | 952 }}); 953 0x6C: FailUnimpl::fxor(); 954 0x6D: FailUnimpl::fxors(); 955 0x6E: FailUnimpl::fnand(); 956 0x6F: FailUnimpl::fnands(); 957 0x70: FailUnimpl::fand(); 958 0x71: FailUnimpl::fands(); 959 0x72: FailUnimpl::fxnor(); 960 0x73: FailUnimpl::fxnors(); |
961 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 962 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); | 961 0x74: FpBasic::fsrc1({{Frd_udw = Frs1_udw;}}); 962 0x75: FpBasic::fsrc1s({{Frds_uw = Frs1s_uw;}}); |
963 0x76: FailUnimpl::fornot2(); 964 0x77: FailUnimpl::fornot2s(); | 963 0x76: FailUnimpl::fornot2(); 964 0x77: FailUnimpl::fornot2s(); |
965 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 966 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); | 965 0x78: FpBasic::fsrc2({{Frd_udw = Frs2_udw;}}); 966 0x79: FpBasic::fsrc2s({{Frds_uw = Frs2s_uw;}}); |
967 0x7A: FailUnimpl::fornot1(); 968 0x7B: FailUnimpl::fornot1s(); 969 0x7C: FailUnimpl::for(); 970 0x7D: FailUnimpl::fors(); | 967 0x7A: FailUnimpl::fornot1(); 968 0x7B: FailUnimpl::fornot1s(); 969 0x7C: FailUnimpl::for(); 970 0x7D: FailUnimpl::fors(); |
971 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 972 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); | 971 0x7E: FpBasic::fone({{Frd_udw = std::numeric_limits<uint64_t>::max();}}); 972 0x7F: FpBasic::fones({{Frds_uw = std::numeric_limits<uint32_t>::max();}}); |
973 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 974 0x81: FailUnimpl::siam(); 975 } 976 // M5 special opcodes use the reserved IMPDEP2A opcode space 977 0x37: decode M5FUNC { 978 format BasicOperate { 979 // we have 7 bits of space here to play with... 980 0x21: m5exit({{ --- 113 unchanged lines hidden (view full) --- 1094 NNPC = Tnpc; 1095 Tl = Tl - 1; 1096 }}, checkTl=true); 1097 } 1098 } 1099 } 1100 0x3: decode OP3 { 1101 format Load { | 973 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 974 0x81: FailUnimpl::siam(); 975 } 976 // M5 special opcodes use the reserved IMPDEP2A opcode space 977 0x37: decode M5FUNC { 978 format BasicOperate { 979 // we have 7 bits of space here to play with... 980 0x21: m5exit({{ --- 113 unchanged lines hidden (view full) --- 1094 NNPC = Tnpc; 1095 Tl = Tl - 1; 1096 }}, checkTl=true); 1097 } 1098 } 1099 } 1100 0x3: decode OP3 { 1101 format Load { |
1102 0x00: lduw({{Rd = Mem.uw;}}); 1103 0x01: ldub({{Rd = Mem.ub;}}); 1104 0x02: lduh({{Rd = Mem.uhw;}}); | 1102 0x00: lduw({{Rd = Mem_uw;}}); 1103 0x01: ldub({{Rd = Mem_ub;}}); 1104 0x02: lduh({{Rd = Mem_uhw;}}); |
1105 0x03: ldtw({{ | 1105 0x03: ldtw({{ |
1106 RdLow = (Mem.tuw).a; 1107 RdHigh = (Mem.tuw).b; | 1106 RdLow = (Mem_tuw).a; 1107 RdHigh = (Mem_tuw).b; |
1108 }}); 1109 } 1110 format Store { | 1108 }}); 1109 } 1110 format Store { |
1111 0x04: stw({{Mem.uw = Rd.sw;}}); 1112 0x05: stb({{Mem.ub = Rd.sb;}}); 1113 0x06: sth({{Mem.uhw = Rd.shw;}}); | 1111 0x04: stw({{Mem_uw = Rd_sw;}}); 1112 0x05: stb({{Mem_ub = Rd_sb;}}); 1113 0x06: sth({{Mem_uhw = Rd_shw;}}); |
1114 0x07: sttw({{ 1115 // This temporary needs to be here so that the parser 1116 // will correctly identify this instruction as a store. 1117 // It's probably either the parenthesis or referencing 1118 // the member variable that throws confuses it. 1119 Twin32_t temp; 1120 temp.a = RdLow<31:0>; 1121 temp.b = RdHigh<31:0>; | 1114 0x07: sttw({{ 1115 // This temporary needs to be here so that the parser 1116 // will correctly identify this instruction as a store. 1117 // It's probably either the parenthesis or referencing 1118 // the member variable that throws confuses it. 1119 Twin32_t temp; 1120 temp.a = RdLow<31:0>; 1121 temp.b = RdHigh<31:0>; |
1122 Mem.tuw = temp; | 1122 Mem_tuw = temp; |
1123 }}); 1124 } 1125 format Load { | 1123 }}); 1124 } 1125 format Load { |
1126 0x08: ldsw({{Rd = Mem.sw;}}); 1127 0x09: ldsb({{Rd = Mem.sb;}}); 1128 0x0A: ldsh({{Rd = Mem.shw;}}); 1129 0x0B: ldx({{Rd = Mem.sdw;}}); | 1126 0x08: ldsw({{Rd = Mem_sw;}}); 1127 0x09: ldsb({{Rd = Mem_sb;}}); 1128 0x0A: ldsh({{Rd = Mem_shw;}}); 1129 0x0B: ldx({{Rd = Mem_sdw;}}); |
1130 } | 1130 } |
1131 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, | 1131 0x0D: Swap::ldstub({{Mem_ub = 0xFF;}}, |
1132 {{ 1133 uint8_t tmp = mem_data; | 1132 {{ 1133 uint8_t tmp = mem_data; |
1134 Rd.ub = tmp; | 1134 Rd_ub = tmp; |
1135 }}, MEM_SWAP); | 1135 }}, MEM_SWAP); |
1136 0x0E: Store::stx({{Mem.udw = Rd}}); 1137 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, | 1136 0x0E: Store::stx({{Mem_udw = Rd}}); 1137 0x0F: Swap::swap({{Mem_uw = Rd_uw}}, |
1138 {{ 1139 uint32_t tmp = mem_data; | 1138 {{ 1139 uint32_t tmp = mem_data; |
1140 Rd.uw = tmp; | 1140 Rd_uw = tmp; |
1141 }}, MEM_SWAP); 1142 format LoadAlt { | 1141 }}, MEM_SWAP); 1142 format LoadAlt { |
1143 0x10: lduwa({{Rd = Mem.uw;}}); 1144 0x11: lduba({{Rd = Mem.ub;}}); 1145 0x12: lduha({{Rd = Mem.uhw;}}); | 1143 0x10: lduwa({{Rd = Mem_uw;}}); 1144 0x11: lduba({{Rd = Mem_ub;}}); 1145 0x12: lduha({{Rd = Mem_uhw;}}); |
1146 0x13: decode EXT_ASI { 1147 // ASI_LDTD_AIUP 1148 0x22: TwinLoad::ldtx_aiup( | 1146 0x13: decode EXT_ASI { 1147 // ASI_LDTD_AIUP 1148 0x22: TwinLoad::ldtx_aiup( |
1149 {{RdLow.udw = (Mem.tudw).a; 1150 RdHigh.udw = (Mem.tudw).b;}}); | 1149 {{RdLow_udw = (Mem_tudw).a; 1150 RdHigh_udw = (Mem_tudw).b;}}); |
1151 // ASI_LDTD_AIUS 1152 0x23: TwinLoad::ldtx_aius( | 1151 // ASI_LDTD_AIUS 1152 0x23: TwinLoad::ldtx_aius( |
1153 {{RdLow.udw = (Mem.tudw).a; 1154 RdHigh.udw = (Mem.tudw).b;}}); | 1153 {{RdLow_udw = (Mem_tudw).a; 1154 RdHigh_udw = (Mem_tudw).b;}}); |
1155 // ASI_QUAD_LDD 1156 0x24: TwinLoad::ldtx_quad_ldd( | 1155 // ASI_QUAD_LDD 1156 0x24: TwinLoad::ldtx_quad_ldd( |
1157 {{RdLow.udw = (Mem.tudw).a; 1158 RdHigh.udw = (Mem.tudw).b;}}); | 1157 {{RdLow_udw = (Mem_tudw).a; 1158 RdHigh_udw = (Mem_tudw).b;}}); |
1159 // ASI_LDTX_REAL 1160 0x26: TwinLoad::ldtx_real( | 1159 // ASI_LDTX_REAL 1160 0x26: TwinLoad::ldtx_real( |
1161 {{RdLow.udw = (Mem.tudw).a; 1162 RdHigh.udw = (Mem.tudw).b;}}); | 1161 {{RdLow_udw = (Mem_tudw).a; 1162 RdHigh_udw = (Mem_tudw).b;}}); |
1163 // ASI_LDTX_N 1164 0x27: TwinLoad::ldtx_n( | 1163 // ASI_LDTX_N 1164 0x27: TwinLoad::ldtx_n( |
1165 {{RdLow.udw = (Mem.tudw).a; 1166 RdHigh.udw = (Mem.tudw).b;}}); | 1165 {{RdLow_udw = (Mem_tudw).a; 1166 RdHigh_udw = (Mem_tudw).b;}}); |
1167 // ASI_LDTX_AIUP_L 1168 0x2A: TwinLoad::ldtx_aiup_l( | 1167 // ASI_LDTX_AIUP_L 1168 0x2A: TwinLoad::ldtx_aiup_l( |
1169 {{RdLow.udw = (Mem.tudw).a; 1170 RdHigh.udw = (Mem.tudw).b;}}); | 1169 {{RdLow_udw = (Mem_tudw).a; 1170 RdHigh_udw = (Mem_tudw).b;}}); |
1171 // ASI_LDTX_AIUS_L 1172 0x2B: TwinLoad::ldtx_aius_l( | 1171 // ASI_LDTX_AIUS_L 1172 0x2B: TwinLoad::ldtx_aius_l( |
1173 {{RdLow.udw = (Mem.tudw).a; 1174 RdHigh.udw = (Mem.tudw).b;}}); | 1173 {{RdLow_udw = (Mem_tudw).a; 1174 RdHigh_udw = (Mem_tudw).b;}}); |
1175 // ASI_LDTX_L 1176 0x2C: TwinLoad::ldtx_l( | 1175 // ASI_LDTX_L 1176 0x2C: TwinLoad::ldtx_l( |
1177 {{RdLow.udw = (Mem.tudw).a; 1178 RdHigh.udw = (Mem.tudw).b;}}); | 1177 {{RdLow_udw = (Mem_tudw).a; 1178 RdHigh_udw = (Mem_tudw).b;}}); |
1179 // ASI_LDTX_REAL_L 1180 0x2E: TwinLoad::ldtx_real_l( | 1179 // ASI_LDTX_REAL_L 1180 0x2E: TwinLoad::ldtx_real_l( |
1181 {{RdLow.udw = (Mem.tudw).a; 1182 RdHigh.udw = (Mem.tudw).b;}}); | 1181 {{RdLow_udw = (Mem_tudw).a; 1182 RdHigh_udw = (Mem_tudw).b;}}); |
1183 // ASI_LDTX_N_L 1184 0x2F: TwinLoad::ldtx_n_l( | 1183 // ASI_LDTX_N_L 1184 0x2F: TwinLoad::ldtx_n_l( |
1185 {{RdLow.udw = (Mem.tudw).a; 1186 RdHigh.udw = (Mem.tudw).b;}}); | 1185 {{RdLow_udw = (Mem_tudw).a; 1186 RdHigh_udw = (Mem_tudw).b;}}); |
1187 // ASI_LDTX_P 1188 0xE2: TwinLoad::ldtx_p( | 1187 // ASI_LDTX_P 1188 0xE2: TwinLoad::ldtx_p( |
1189 {{RdLow.udw = (Mem.tudw).a; 1190 RdHigh.udw = (Mem.tudw).b;}}); | 1189 {{RdLow_udw = (Mem_tudw).a; 1190 RdHigh_udw = (Mem_tudw).b;}}); |
1191 // ASI_LDTX_S 1192 0xE3: TwinLoad::ldtx_s( | 1191 // ASI_LDTX_S 1192 0xE3: TwinLoad::ldtx_s( |
1193 {{RdLow.udw = (Mem.tudw).a; 1194 RdHigh.udw = (Mem.tudw).b;}}); | 1193 {{RdLow_udw = (Mem_tudw).a; 1194 RdHigh_udw = (Mem_tudw).b;}}); |
1195 // ASI_LDTX_PL 1196 0xEA: TwinLoad::ldtx_pl( | 1195 // ASI_LDTX_PL 1196 0xEA: TwinLoad::ldtx_pl( |
1197 {{RdLow.udw = (Mem.tudw).a; 1198 RdHigh.udw = (Mem.tudw).b;}}); | 1197 {{RdLow_udw = (Mem_tudw).a; 1198 RdHigh_udw = (Mem_tudw).b;}}); |
1199 // ASI_LDTX_SL 1200 0xEB: TwinLoad::ldtx_sl( | 1199 // ASI_LDTX_SL 1200 0xEB: TwinLoad::ldtx_sl( |
1201 {{RdLow.udw = (Mem.tudw).a; 1202 RdHigh.udw = (Mem.tudw).b;}}); | 1201 {{RdLow_udw = (Mem_tudw).a; 1202 RdHigh_udw = (Mem_tudw).b;}}); |
1203 default: ldtwa({{ | 1203 default: ldtwa({{ |
1204 RdLow = (Mem.tuw).a; 1205 RdHigh = (Mem.tuw).b;}}); | 1204 RdLow = (Mem_tuw).a; 1205 RdHigh = (Mem_tuw).b;}}); |
1206 } 1207 } 1208 format StoreAlt { | 1206 } 1207 } 1208 format StoreAlt { |
1209 0x14: stwa({{Mem.uw = Rd;}}); 1210 0x15: stba({{Mem.ub = Rd;}}); 1211 0x16: stha({{Mem.uhw = Rd;}}); | 1209 0x14: stwa({{Mem_uw = Rd;}}); 1210 0x15: stba({{Mem_ub = Rd;}}); 1211 0x16: stha({{Mem_uhw = Rd;}}); |
1212 0x17: sttwa({{ 1213 // This temporary needs to be here so that the parser 1214 // will correctly identify this instruction as a store. 1215 // It's probably either the parenthesis or referencing 1216 // the member variable that throws confuses it. 1217 Twin32_t temp; 1218 temp.a = RdLow<31:0>; 1219 temp.b = RdHigh<31:0>; | 1212 0x17: sttwa({{ 1213 // This temporary needs to be here so that the parser 1214 // will correctly identify this instruction as a store. 1215 // It's probably either the parenthesis or referencing 1216 // the member variable that throws confuses it. 1217 Twin32_t temp; 1218 temp.a = RdLow<31:0>; 1219 temp.b = RdHigh<31:0>; |
1220 Mem.tuw = temp; | 1220 Mem_tuw = temp; |
1221 }}); 1222 } 1223 format LoadAlt { | 1221 }}); 1222 } 1223 format LoadAlt { |
1224 0x18: ldswa({{Rd = Mem.sw;}}); 1225 0x19: ldsba({{Rd = Mem.sb;}}); 1226 0x1A: ldsha({{Rd = Mem.shw;}}); 1227 0x1B: ldxa({{Rd = Mem.sdw;}}); | 1224 0x18: ldswa({{Rd = Mem_sw;}}); 1225 0x19: ldsba({{Rd = Mem_sb;}}); 1226 0x1A: ldsha({{Rd = Mem_shw;}}); 1227 0x1B: ldxa({{Rd = Mem_sdw;}}); |
1228 } | 1228 } |
1229 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, | 1229 0x1D: SwapAlt::ldstuba({{Mem_ub = 0xFF;}}, |
1230 {{ 1231 uint8_t tmp = mem_data; | 1230 {{ 1231 uint8_t tmp = mem_data; |
1232 Rd.ub = tmp; | 1232 Rd_ub = tmp; |
1233 }}, MEM_SWAP); | 1233 }}, MEM_SWAP); |
1234 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 1235 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, | 1234 0x1E: StoreAlt::stxa({{Mem_udw = Rd}}); 1235 0x1F: SwapAlt::swapa({{Mem_uw = Rd_uw}}, |
1236 {{ 1237 uint32_t tmp = mem_data; | 1236 {{ 1237 uint32_t tmp = mem_data; |
1238 Rd.uw = tmp; | 1238 Rd_uw = tmp; |
1239 }}, MEM_SWAP); 1240 1241 format Trap { | 1239 }}, MEM_SWAP); 1240 1241 format Trap { |
1242 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); | 1242 0x20: Load::ldf({{Frds_uw = Mem_uw;}}); |
1243 0x21: decode RD { 1244 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1245 if (fault) 1246 return fault; | 1243 0x21: decode RD { 1244 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1245 if (fault) 1246 return fault; |
1247 Fsr = Mem.uw | Fsr<63:32>;}}); | 1247 Fsr = Mem_uw | Fsr<63:32>;}}); |
1248 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1249 if (fault) 1250 return fault; | 1248 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1249 if (fault) 1250 return fault; |
1251 Fsr = Mem.udw;}}); | 1251 Fsr = Mem_udw;}}); |
1252 default: FailUnimpl::ldfsrOther(); 1253 } 1254 0x22: ldqf({{fault = new FpDisabled;}}); | 1252 default: FailUnimpl::ldfsrOther(); 1253 } 1254 0x22: ldqf({{fault = new FpDisabled;}}); |
1255 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1256 0x24: Store::stf({{Mem.uw = Frds.uw;}}); | 1255 0x23: Load::lddf({{Frd_udw = Mem_udw;}}); 1256 0x24: Store::stf({{Mem_uw = Frds_uw;}}); |
1257 0x25: decode RD { 1258 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 1259 if (fault) 1260 return fault; | 1257 0x25: decode RD { 1258 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 1259 if (fault) 1260 return fault; |
1261 Mem.uw = Fsr<31:0>;}}); | 1261 Mem_uw = Fsr<31:0>;}}); |
1262 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 1263 if (fault) 1264 return fault; | 1262 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 1263 if (fault) 1264 return fault; |
1265 Mem.udw = Fsr;}}); | 1265 Mem_udw = Fsr;}}); |
1266 default: FailUnimpl::stfsrOther(); 1267 } 1268 0x26: stqf({{fault = new FpDisabled;}}); | 1266 default: FailUnimpl::stfsrOther(); 1267 } 1268 0x26: stqf({{fault = new FpDisabled;}}); |
1269 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); | 1269 0x27: Store::stdf({{Mem_udw = Frd_udw;}}); |
1270 0x2D: Nop::prefetch({{ }}); | 1270 0x2D: Nop::prefetch({{ }}); |
1271 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); | 1271 0x30: LoadAlt::ldfa({{Frds_uw = Mem_uw;}}); |
1272 0x32: ldqfa({{fault = new FpDisabled;}}); 1273 format LoadAlt { 1274 0x33: decode EXT_ASI { 1275 // ASI_NUCLEUS 1276 0x04: FailUnimpl::lddfa_n(); 1277 // ASI_NUCLEUS_LITTLE 1278 0x0C: FailUnimpl::lddfa_nl(); 1279 // ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1315 0x16: FailUnimpl::ldblockf_aiup(); 1316 // ASI_BLOCK_AS_IF_USER_SECONDARY 1317 0x17: FailUnimpl::ldblockf_aius(); 1318 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1319 0x1E: FailUnimpl::ldblockf_aiupl(); 1320 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1321 0x1F: FailUnimpl::ldblockf_aiusl(); 1322 // ASI_BLOCK_PRIMARY | 1272 0x32: ldqfa({{fault = new FpDisabled;}}); 1273 format LoadAlt { 1274 0x33: decode EXT_ASI { 1275 // ASI_NUCLEUS 1276 0x04: FailUnimpl::lddfa_n(); 1277 // ASI_NUCLEUS_LITTLE 1278 0x0C: FailUnimpl::lddfa_nl(); 1279 // ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1315 0x16: FailUnimpl::ldblockf_aiup(); 1316 // ASI_BLOCK_AS_IF_USER_SECONDARY 1317 0x17: FailUnimpl::ldblockf_aius(); 1318 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1319 0x1E: FailUnimpl::ldblockf_aiupl(); 1320 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1321 0x1F: FailUnimpl::ldblockf_aiusl(); 1322 // ASI_BLOCK_PRIMARY |
1323 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); | 1323 0xF0: ldblockf_p({{Frd_N_udw = Mem_udw;}}); |
1324 // ASI_BLOCK_SECONDARY 1325 0xF1: FailUnimpl::ldblockf_s(); 1326 // ASI_BLOCK_PRIMARY_LITTLE 1327 0xF8: FailUnimpl::ldblockf_pl(); 1328 // ASI_BLOCK_SECONDARY_LITTLE 1329 0xF9: FailUnimpl::ldblockf_sl(); 1330 } 1331 --- 14 unchanged lines hidden (view full) --- 1346 0xDA: FailUnimpl::ldshortf_16pl(); 1347 // ASI_FL16_SECONDARY_LITTLE 1348 0xDB: FailUnimpl::ldshortf_16sl(); 1349 // Not an ASI which is legal with lddfa 1350 default: Trap::lddfa_bad_asi( 1351 {{fault = new DataAccessException;}}); 1352 } 1353 } | 1324 // ASI_BLOCK_SECONDARY 1325 0xF1: FailUnimpl::ldblockf_s(); 1326 // ASI_BLOCK_PRIMARY_LITTLE 1327 0xF8: FailUnimpl::ldblockf_pl(); 1328 // ASI_BLOCK_SECONDARY_LITTLE 1329 0xF9: FailUnimpl::ldblockf_sl(); 1330 } 1331 --- 14 unchanged lines hidden (view full) --- 1346 0xDA: FailUnimpl::ldshortf_16pl(); 1347 // ASI_FL16_SECONDARY_LITTLE 1348 0xDB: FailUnimpl::ldshortf_16sl(); 1349 // Not an ASI which is legal with lddfa 1350 default: Trap::lddfa_bad_asi( 1351 {{fault = new DataAccessException;}}); 1352 } 1353 } |
1354 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); | 1354 0x34: Store::stfa({{Mem_uw = Frds_uw;}}); |
1355 0x36: stqfa({{fault = new FpDisabled;}}); 1356 format StoreAlt { 1357 0x37: decode EXT_ASI { 1358 // ASI_NUCLEUS 1359 0x04: FailUnimpl::stdfa_n(); 1360 // ASI_NUCLEUS_LITTLE 1361 0x0C: FailUnimpl::stdfa_nl(); 1362 // ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1398 0x16: FailUnimpl::stblockf_aiup(); 1399 // ASI_BLOCK_AS_IF_USER_SECONDARY 1400 0x17: FailUnimpl::stblockf_aius(); 1401 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1402 0x1E: FailUnimpl::stblockf_aiupl(); 1403 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1404 0x1F: FailUnimpl::stblockf_aiusl(); 1405 // ASI_BLOCK_PRIMARY | 1355 0x36: stqfa({{fault = new FpDisabled;}}); 1356 format StoreAlt { 1357 0x37: decode EXT_ASI { 1358 // ASI_NUCLEUS 1359 0x04: FailUnimpl::stdfa_n(); 1360 // ASI_NUCLEUS_LITTLE 1361 0x0C: FailUnimpl::stdfa_nl(); 1362 // ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1398 0x16: FailUnimpl::stblockf_aiup(); 1399 // ASI_BLOCK_AS_IF_USER_SECONDARY 1400 0x17: FailUnimpl::stblockf_aius(); 1401 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1402 0x1E: FailUnimpl::stblockf_aiupl(); 1403 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1404 0x1F: FailUnimpl::stblockf_aiusl(); 1405 // ASI_BLOCK_PRIMARY |
1406 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); | 1406 0xF0: stblockf_p({{Mem_udw = Frd_N_udw;}}); |
1407 // ASI_BLOCK_SECONDARY 1408 0xF1: FailUnimpl::stblockf_s(); 1409 // ASI_BLOCK_PRIMARY_LITTLE 1410 0xF8: FailUnimpl::stblockf_pl(); 1411 // ASI_BLOCK_SECONDARY_LITTLE 1412 0xF9: FailUnimpl::stblockf_sl(); 1413 } 1414 --- 15 unchanged lines hidden (view full) --- 1430 // ASI_FL16_SECONDARY_LITTLE 1431 0xDB: FailUnimpl::stshortf_16sl(); 1432 // Not an ASI which is legal with lddfa 1433 default: Trap::stdfa_bad_asi( 1434 {{fault = new DataAccessException;}}); 1435 } 1436 } 1437 0x3C: CasAlt::casa({{ | 1407 // ASI_BLOCK_SECONDARY 1408 0xF1: FailUnimpl::stblockf_s(); 1409 // ASI_BLOCK_PRIMARY_LITTLE 1410 0xF8: FailUnimpl::stblockf_pl(); 1411 // ASI_BLOCK_SECONDARY_LITTLE 1412 0xF9: FailUnimpl::stblockf_sl(); 1413 } 1414 --- 15 unchanged lines hidden (view full) --- 1430 // ASI_FL16_SECONDARY_LITTLE 1431 0xDB: FailUnimpl::stshortf_16sl(); 1432 // Not an ASI which is legal with lddfa 1433 default: Trap::stdfa_bad_asi( 1434 {{fault = new DataAccessException;}}); 1435 } 1436 } 1437 0x3C: CasAlt::casa({{ |
1438 mem_data = htog(Rs2.uw); 1439 Mem.uw = Rd.uw;}}, | 1438 mem_data = htog(Rs2_uw); 1439 Mem_uw = Rd_uw;}}, |
1440 {{ 1441 uint32_t tmp = mem_data; | 1440 {{ 1441 uint32_t tmp = mem_data; |
1442 Rd.uw = tmp; | 1442 Rd_uw = tmp; |
1443 }}, MEM_SWAP_COND); 1444 0x3D: Nop::prefetcha({{ }}); 1445 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); | 1443 }}, MEM_SWAP_COND); 1444 0x3D: Nop::prefetcha({{ }}); 1445 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); |
1446 Mem.udw = Rd.udw; }}, 1447 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); | 1446 Mem_udw = Rd_udw; }}, 1447 {{ Rd_udw = mem_data; }}, MEM_SWAP_COND); |
1448 } 1449 } 1450} | 1448 } 1449 } 1450} |