decoder.isa (7784:e7649570ff3a) decoder.isa (7790:9df469679ac7)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 // bpcc
45 0x1: decode COND2
46 {
47 // Branch Always
48 0x8: bpa(19, annul_code={{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 // bpcc
45 0x1: decode COND2
46 {
47 // Branch Always
48 0x8: bpa(19, annul_code={{
49 SparcISA::PCState pc = PCS;
50 pc.npc(pc.pc() + disp);
51 pc.nnpc(pc.npc() + 4);
52 PCS = pc;
49 NPC = PC + disp;
50 NNPC = PC + disp + 4;
53 }});
54 // Branch Never
55 0x0: bpn(19, {{;}},
56 annul_code={{
51 }});
52 // Branch Never
53 0x0: bpn(19, {{;}},
54 annul_code={{
57 SparcISA::PCState pc = PCS;
58 pc.nnpc(pc.npc() + 8);
59 pc.npc(pc.npc() + 4);
60 PCS = pc;
55 NNPC = NPC + 8;
56 NPC = NPC + 4;
61 }});
62 default: decode BPCC
63 {
64 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
65 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
66 }
67 }
68 // bicc
69 0x2: decode COND2
70 {
71 // Branch Always
72 0x8: ba(22, annul_code={{
57 }});
58 default: decode BPCC
59 {
60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
62 }
63 }
64 // bicc
65 0x2: decode COND2
66 {
67 // Branch Always
68 0x8: ba(22, annul_code={{
73 SparcISA::PCState pc = PCS;
74 pc.npc(pc.pc() + disp);
75 pc.nnpc(pc.npc() + 4);
76 PCS = pc;
69 NPC = PC + disp;
70 NNPC = PC + disp + 4;
77 }});
78 // Branch Never
79 0x0: bn(22, {{;}},
80 annul_code={{
71 }});
72 // Branch Never
73 0x0: bn(22, {{;}},
74 annul_code={{
81 SparcISA::PCState pc = PCS;
82 pc.nnpc(pc.npc() + 8);
83 pc.npc(pc.npc() + 4);
84 PCS = pc;
75 NNPC = NPC + 8;
76 NPC = NPC + 4;
85 }});
86 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
87 }
88 }
89 0x3: decode RCOND2
90 {
91 format BranchSplit
92 {

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100 }
101 // SETHI (or NOP if rd == 0 and imm == 0)
102 0x4: SetHi::sethi({{Rd.udw = imm;}});
103 // fbpfcc
104 0x5: decode COND2 {
105 format BranchN {
106 // Branch Always
107 0x8: fbpa(22, annul_code={{
77 }});
78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
79 }
80 }
81 0x3: decode RCOND2
82 {
83 format BranchSplit
84 {

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92 }
93 // SETHI (or NOP if rd == 0 and imm == 0)
94 0x4: SetHi::sethi({{Rd.udw = imm;}});
95 // fbpfcc
96 0x5: decode COND2 {
97 format BranchN {
98 // Branch Always
99 0x8: fbpa(22, annul_code={{
108 SparcISA::PCState pc = PCS;
109 pc.npc(pc.pc() + disp);
110 pc.nnpc(pc.npc() + 4);
111 PCS = pc;
100 NPC = PC + disp;
101 NNPC = PC + disp + 4;
112 }});
113 // Branch Never
114 0x0: fbpn(22, {{;}},
115 annul_code={{
102 }});
103 // Branch Never
104 0x0: fbpn(22, {{;}},
105 annul_code={{
116 SparcISA::PCState pc = PCS;
117 pc.nnpc(pc.npc() + 8);
118 pc.npc(pc.npc() + 4);
119 PCS = pc;
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
120 }});
121 default: decode BPCC {
122 0x0: fbpfcc0(19, test=
123 {{passesFpCondition(Fsr<11:10>, COND2)}});
124 0x1: fbpfcc1(19, test=
125 {{passesFpCondition(Fsr<33:32>, COND2)}});
126 0x2: fbpfcc2(19, test=
127 {{passesFpCondition(Fsr<35:34>, COND2)}});
128 0x3: fbpfcc3(19, test=
129 {{passesFpCondition(Fsr<37:36>, COND2)}});
130 }
131 }
132 }
133 // fbfcc
134 0x6: decode COND2 {
135 format BranchN {
136 // Branch Always
137 0x8: fba(22, annul_code={{
108 }});
109 default: decode BPCC {
110 0x0: fbpfcc0(19, test=
111 {{passesFpCondition(Fsr<11:10>, COND2)}});
112 0x1: fbpfcc1(19, test=
113 {{passesFpCondition(Fsr<33:32>, COND2)}});
114 0x2: fbpfcc2(19, test=
115 {{passesFpCondition(Fsr<35:34>, COND2)}});
116 0x3: fbpfcc3(19, test=
117 {{passesFpCondition(Fsr<37:36>, COND2)}});
118 }
119 }
120 }
121 // fbfcc
122 0x6: decode COND2 {
123 format BranchN {
124 // Branch Always
125 0x8: fba(22, annul_code={{
138 SparcISA::PCState pc = PCS;
139 pc.npc(pc.pc() + disp);
140 pc.nnpc(pc.npc() + 4);
141 PCS = pc;
126 NPC = PC + disp;
127 NNPC = PC + disp + 4;
142 }});
143 // Branch Never
144 0x0: fbn(22, {{;}},
145 annul_code={{
128 }});
129 // Branch Never
130 0x0: fbn(22, {{;}},
131 annul_code={{
146 SparcISA::PCState pc = PCS;
147 pc.nnpc(pc.npc() + 8);
148 pc.npc(pc.npc() + 4);
149 PCS = pc;
132 NNPC = NPC + 8;
133 NPC = NPC + 4;
150 }});
151 default: fbfcc(22, test=
152 {{passesFpCondition(Fsr<11:10>, COND2)}});
153 }
154 }
155 }
156 0x1: BranchN::call(30, {{
134 }});
135 default: fbfcc(22, test=
136 {{passesFpCondition(Fsr<11:10>, COND2)}});
137 }
138 }
139 }
140 0x1: BranchN::call(30, {{
157 SparcISA::PCState pc = PCS;
158 if (Pstate<3:>)
141 if (Pstate<3:>)
159 R15 = (pc.pc())<31:0>;
142 R15 = (PC)<31:0>;
160 else
143 else
161 R15 = pc.pc();
162 pc.nnpc(R15 + disp);
163 PCS = pc;
144 R15 = PC;
145 NNPC = R15 + disp;
164 }});
165 0x2: decode OP3 {
166 format IntOp {
167 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
168 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
169 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
170 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
171 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});

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342 }
343 0x28: decode RS1 {
344 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
345 // 1 should cause an illegal instruction exception
346 0x02: NoPriv::rdccr({{Rd = Ccr;}});
347 0x03: NoPriv::rdasi({{Rd = Asi;}});
348 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
349 0x05: NoPriv::rdpc({{
146 }});
147 0x2: decode OP3 {
148 format IntOp {
149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});

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324 }
325 0x28: decode RS1 {
326 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
327 // 1 should cause an illegal instruction exception
328 0x02: NoPriv::rdccr({{Rd = Ccr;}});
329 0x03: NoPriv::rdasi({{Rd = Asi;}});
330 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
331 0x05: NoPriv::rdpc({{
350 SparcISA::PCState pc = PCS;
351 if (Pstate<3:>)
332 if (Pstate<3:>)
352 Rd = (pc.pc())<31:0>;
333 Rd = (PC)<31:0>;
353 else
334 else
354 Rd = pc.pc();
335 Rd = PC;
355 }});
356 0x06: NoPriv::rdfprs({{
357 // Wait for all fpops to finish.
358 Rd = Fprs;
359 }});
360 // 7-14 should cause an illegal instruction exception
361 0x0F: decode I {
362 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);

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994 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
995 0x81: FailUnimpl::siam();
996 }
997 // M5 special opcodes use the reserved IMPDEP2A opcode space
998 0x37: decode M5FUNC {
999#if FULL_SYSTEM
1000 format BasicOperate {
1001 // we have 7 bits of space here to play with...
336 }});
337 0x06: NoPriv::rdfprs({{
338 // Wait for all fpops to finish.
339 Rd = Fprs;
340 }});
341 // 7-14 should cause an illegal instruction exception
342 0x0F: decode I {
343 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);

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975 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
976 0x81: FailUnimpl::siam();
977 }
978 // M5 special opcodes use the reserved IMPDEP2A opcode space
979 0x37: decode M5FUNC {
980#if FULL_SYSTEM
981 format BasicOperate {
982 // we have 7 bits of space here to play with...
1002 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
1003 }}, No_OpClass, IsNonSpeculative);
983 0x21: m5exit({{
984 PseudoInst::m5exit(xc->tcBase(), O0);
985 }}, No_OpClass, IsNonSpeculative);
1004 0x50: m5readfile({{
986 0x50: m5readfile({{
1005 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
1006 }}, IsNonSpeculative);
1007 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
1008 }}, IsNonSpeculative);
987 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
988 }}, IsNonSpeculative);
989 0x51: m5break({{
990 PseudoInst::debugbreak(xc->tcBase());
991 }}, IsNonSpeculative);
1009 0x54: m5panic({{
992 0x54: m5panic({{
1010 SparcISA::PCState pc = PCS;
1011 panic("M5 panic instruction called at pc=%#x.", pc.pc());
1012 }}, No_OpClass, IsNonSpeculative);
993 panic("M5 panic instruction called at pc = %#x.", PC);
994 }}, No_OpClass, IsNonSpeculative);
1013 }
1014#endif
1015 default: Trap::impdep2({{fault = new IllegalInstruction;}});
1016 }
1017 0x38: Branch::jmpl({{
1018 Addr target = Rs1 + Rs2_or_imm13;
1019 if (target & 0x3) {
1020 fault = new MemAddressNotAligned;
1021 } else {
995 }
996#endif
997 default: Trap::impdep2({{fault = new IllegalInstruction;}});
998 }
999 0x38: Branch::jmpl({{
1000 Addr target = Rs1 + Rs2_or_imm13;
1001 if (target & 0x3) {
1002 fault = new MemAddressNotAligned;
1003 } else {
1022 SparcISA::PCState pc = PCS;
1023 if (Pstate<3:>)
1004 if (Pstate<3:>)
1024 Rd = (pc.pc())<31:0>;
1005 Rd = (PC)<31:0>;
1025 else
1006 else
1026 Rd = pc.pc();
1027 pc.nnpc(target);
1028 PCS = pc;
1007 Rd = PC;
1008 NNPC = target;
1029 }
1030 }});
1031 0x39: Branch::return({{
1032 Addr target = Rs1 + Rs2_or_imm13;
1033 if (fault == NoFault) {
1034 // Check for fills which are higher priority than alignment
1035 // faults.
1036 if (Canrestore == 0) {
1037 if (Otherwin)
1038 fault = new FillNOther(4*Wstate<5:3>);
1039 else
1040 fault = new FillNNormal(4*Wstate<2:0>);
1041 } else if (target & 0x3) { // Check for alignment faults
1042 fault = new MemAddressNotAligned;
1043 } else {
1009 }
1010 }});
1011 0x39: Branch::return({{
1012 Addr target = Rs1 + Rs2_or_imm13;
1013 if (fault == NoFault) {
1014 // Check for fills which are higher priority than alignment
1015 // faults.
1016 if (Canrestore == 0) {
1017 if (Otherwin)
1018 fault = new FillNOther(4*Wstate<5:3>);
1019 else
1020 fault = new FillNNormal(4*Wstate<2:0>);
1021 } else if (target & 0x3) { // Check for alignment faults
1022 fault = new MemAddressNotAligned;
1023 } else {
1044 SparcISA::PCState pc = PCS;
1045 pc.nnpc(target);
1046 PCS = pc;
1024 NNPC = target;
1047 Cwp = (Cwp - 1 + NWindows) % NWindows;
1048 Cansave = Cansave + 1;
1049 Canrestore = Canrestore - 1;
1050 }
1051 }
1052 }});
1053 0x3A: decode CC
1054 {

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1100 0x3E: decode FCN {
1101 0x0: Priv::done({{
1102 Cwp = Tstate<4:0>;
1103 Pstate = Tstate<20:8>;
1104 Asi = Tstate<31:24>;
1105 Ccr = Tstate<39:32>;
1106 Gl = Tstate<42:40>;
1107 Hpstate = Htstate;
1025 Cwp = (Cwp - 1 + NWindows) % NWindows;
1026 Cansave = Cansave + 1;
1027 Canrestore = Canrestore - 1;
1028 }
1029 }
1030 }});
1031 0x3A: decode CC
1032 {

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1078 0x3E: decode FCN {
1079 0x0: Priv::done({{
1080 Cwp = Tstate<4:0>;
1081 Pstate = Tstate<20:8>;
1082 Asi = Tstate<31:24>;
1083 Ccr = Tstate<39:32>;
1084 Gl = Tstate<42:40>;
1085 Hpstate = Htstate;
1108 SparcISA::PCState pc = PCS;
1109 pc.npc(Tnpc);
1110 pc.nnpc(Tnpc + 4);
1111 PCS = pc;
1086 NPC = Tnpc;
1087 NNPC = Tnpc + 4;
1112 Tl = Tl - 1;
1113 }}, checkTl=true);
1114 0x1: Priv::retry({{
1115 Cwp = Tstate<4:0>;
1116 Pstate = Tstate<20:8>;
1117 Asi = Tstate<31:24>;
1118 Ccr = Tstate<39:32>;
1119 Gl = Tstate<42:40>;
1120 Hpstate = Htstate;
1088 Tl = Tl - 1;
1089 }}, checkTl=true);
1090 0x1: Priv::retry({{
1091 Cwp = Tstate<4:0>;
1092 Pstate = Tstate<20:8>;
1093 Asi = Tstate<31:24>;
1094 Ccr = Tstate<39:32>;
1095 Gl = Tstate<42:40>;
1096 Hpstate = Htstate;
1121 SparcISA::PCState pc = PCS;
1122 pc.npc(Tpc);
1123 pc.nnpc(Tnpc);
1124 PCS = pc;
1097 NPC = Tpc;
1098 NNPC = Tnpc;
1125 Tl = Tl - 1;
1126 }}, checkTl=true);
1127 }
1128 }
1129 }
1130 0x3: decode OP3 {
1131 format Load {
1132 0x00: lduw({{Rd = Mem.uw;}});

--- 348 unchanged lines hidden --- 		1099 Tl = Tl - 1;
1100 }}, checkTl=true);
1101 }
1102 }
1103 }
1104 0x3: decode OP3 {
1105 format Load {
1106 0x00: lduw({{Rd = Mem.uw;}});

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