decoder.isa (5095:65cc3a615375) decoder.isa (5096:eb06635e06ac)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1111 }}, MEM_SWAP);
1112 0x0E: Store::stx({{Mem.udw = Rd}});
1113 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
1114 {{
1115 uint32_t tmp = mem_data;
1116 Rd.uw = tmp;
1117 }}, MEM_SWAP);
1118 format LoadAlt {
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1111 }}, MEM_SWAP);
1112 0x0E: Store::stx({{Mem.udw = Rd}});
1113 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
1114 {{
1115 uint32_t tmp = mem_data;
1116 Rd.uw = tmp;
1117 }}, MEM_SWAP);
1118 format LoadAlt {
1119 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1120 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1121 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1119 0x10: lduwa({{Rd = Mem.uw;}});
1120 0x11: lduba({{Rd = Mem.ub;}});
1121 0x12: lduha({{Rd = Mem.uhw;}});
1122 0x13: decode EXT_ASI {
1123 //ASI_LDTD_AIUP
1124 0x22: TwinLoad::ldtx_aiup(
1125 {{RdLow.udw = (Mem.tudw).a;
1122 0x13: decode EXT_ASI {
1123 //ASI_LDTD_AIUP
1124 0x22: TwinLoad::ldtx_aiup(
1125 {{RdLow.udw = (Mem.tudw).a;
1126 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1126 RdHigh.udw = (Mem.tudw).b;}});
1127 //ASI_LDTD_AIUS
1128 0x23: TwinLoad::ldtx_aius(
1129 {{RdLow.udw = (Mem.tudw).a;
1127 //ASI_LDTD_AIUS
1128 0x23: TwinLoad::ldtx_aius(
1129 {{RdLow.udw = (Mem.tudw).a;
1130 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1130 RdHigh.udw = (Mem.tudw).b;}});
1131 //ASI_QUAD_LDD
1132 0x24: TwinLoad::ldtx_quad_ldd(
1133 {{RdLow.udw = (Mem.tudw).a;
1131 //ASI_QUAD_LDD
1132 0x24: TwinLoad::ldtx_quad_ldd(
1133 {{RdLow.udw = (Mem.tudw).a;
1134 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1134 RdHigh.udw = (Mem.tudw).b;}});
1135 //ASI_LDTX_REAL
1136 0x26: TwinLoad::ldtx_real(
1137 {{RdLow.udw = (Mem.tudw).a;
1135 //ASI_LDTX_REAL
1136 0x26: TwinLoad::ldtx_real(
1137 {{RdLow.udw = (Mem.tudw).a;
1138 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1138 RdHigh.udw = (Mem.tudw).b;}});
1139 //ASI_LDTX_N
1140 0x27: TwinLoad::ldtx_n(
1141 {{RdLow.udw = (Mem.tudw).a;
1139 //ASI_LDTX_N
1140 0x27: TwinLoad::ldtx_n(
1141 {{RdLow.udw = (Mem.tudw).a;
1142 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1142 RdHigh.udw = (Mem.tudw).b;}});
1143 //ASI_LDTX_AIUP_L
1144 0x2A: TwinLoad::ldtx_aiup_l(
1145 {{RdLow.udw = (Mem.tudw).a;
1143 //ASI_LDTX_AIUP_L
1144 0x2A: TwinLoad::ldtx_aiup_l(
1145 {{RdLow.udw = (Mem.tudw).a;
1146 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1146 RdHigh.udw = (Mem.tudw).b;}});
1147 //ASI_LDTX_AIUS_L
1148 0x2B: TwinLoad::ldtx_aius_l(
1149 {{RdLow.udw = (Mem.tudw).a;
1147 //ASI_LDTX_AIUS_L
1148 0x2B: TwinLoad::ldtx_aius_l(
1149 {{RdLow.udw = (Mem.tudw).a;
1150 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1150 RdHigh.udw = (Mem.tudw).b;}});
1151 //ASI_LDTX_L
1152 0x2C: TwinLoad::ldtx_l(
1153 {{RdLow.udw = (Mem.tudw).a;
1151 //ASI_LDTX_L
1152 0x2C: TwinLoad::ldtx_l(
1153 {{RdLow.udw = (Mem.tudw).a;
1154 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1154 RdHigh.udw = (Mem.tudw).b;}});
1155 //ASI_LDTX_REAL_L
1156 0x2E: TwinLoad::ldtx_real_l(
1157 {{RdLow.udw = (Mem.tudw).a;
1155 //ASI_LDTX_REAL_L
1156 0x2E: TwinLoad::ldtx_real_l(
1157 {{RdLow.udw = (Mem.tudw).a;
1158 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1158 RdHigh.udw = (Mem.tudw).b;}});
1159 //ASI_LDTX_N_L
1160 0x2F: TwinLoad::ldtx_n_l(
1161 {{RdLow.udw = (Mem.tudw).a;
1159 //ASI_LDTX_N_L
1160 0x2F: TwinLoad::ldtx_n_l(
1161 {{RdLow.udw = (Mem.tudw).a;
1162 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1162 RdHigh.udw = (Mem.tudw).b;}});
1163 //ASI_LDTX_P
1164 0xE2: TwinLoad::ldtx_p(
1165 {{RdLow.udw = (Mem.tudw).a;
1163 //ASI_LDTX_P
1164 0xE2: TwinLoad::ldtx_p(
1165 {{RdLow.udw = (Mem.tudw).a;
1166 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1166 RdHigh.udw = (Mem.tudw).b;}});
1167 //ASI_LDTX_S
1168 0xE3: TwinLoad::ldtx_s(
1169 {{RdLow.udw = (Mem.tudw).a;
1167 //ASI_LDTX_S
1168 0xE3: TwinLoad::ldtx_s(
1169 {{RdLow.udw = (Mem.tudw).a;
1170 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1170 RdHigh.udw = (Mem.tudw).b;}});
1171 //ASI_LDTX_PL
1172 0xEA: TwinLoad::ldtx_pl(
1173 {{RdLow.udw = (Mem.tudw).a;
1171 //ASI_LDTX_PL
1172 0xEA: TwinLoad::ldtx_pl(
1173 {{RdLow.udw = (Mem.tudw).a;
1174 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1174 RdHigh.udw = (Mem.tudw).b;}});
1175 //ASI_LDTX_SL
1176 0xEB: TwinLoad::ldtx_sl(
1177 {{RdLow.udw = (Mem.tudw).a;
1175 //ASI_LDTX_SL
1176 0xEB: TwinLoad::ldtx_sl(
1177 {{RdLow.udw = (Mem.tudw).a;
1178 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1178 RdHigh.udw = (Mem.tudw).b;}});
1179 default: ldtwa({{
1180 RdLow = (Mem.tuw).a;
1179 default: ldtwa({{
1180 RdLow = (Mem.tuw).a;
1181 RdHigh = (Mem.tuw).b;
1182 }}, {{EXT_ASI}});
1181 RdHigh = (Mem.tuw).b;}});
1183 }
1184 }
1185 format StoreAlt {
1182 }
1183 }
1184 format StoreAlt {
1186 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1187 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1188 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1185 0x14: stwa({{Mem.uw = Rd;}});
1186 0x15: stba({{Mem.ub = Rd;}});
1187 0x16: stha({{Mem.uhw = Rd;}});
1189 0x17: sttwa({{
1190 //This temporary needs to be here so that the parser
1191 //will correctly identify this instruction as a store.
1192 //It's probably either the parenthesis or referencing
1193 //the member variable that throws confuses it.
1194 Twin32_t temp;
1195 temp.a = RdLow<31:0>;
1196 temp.b = RdHigh<31:0>;
1197 Mem.tuw = temp;
1188 0x17: sttwa({{
1189 //This temporary needs to be here so that the parser
1190 //will correctly identify this instruction as a store.
1191 //It's probably either the parenthesis or referencing
1192 //the member variable that throws confuses it.
1193 Twin32_t temp;
1194 temp.a = RdLow<31:0>;
1195 temp.b = RdHigh<31:0>;
1196 Mem.tuw = temp;
1198 }}, {{EXT_ASI}});
1197 }});
1199 }
1200 format LoadAlt {
1198 }
1199 format LoadAlt {
1201 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1202 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1203 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1204 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1200 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
1201 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
1202 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
1203 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
1205 }
1206 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
1207 {{
1208 uint8_t tmp = mem_data;
1209 Rd.ub = tmp;
1204 }
1205 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
1206 {{
1207 uint8_t tmp = mem_data;
1208 Rd.ub = tmp;
1210 }}, {{EXT_ASI}}, MEM_SWAP);
1211 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1209 }}, MEM_SWAP);
1210 0x1E: StoreAlt::stxa({{Mem.udw = Rd}});
1212 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
1213 {{
1214 uint32_t tmp = mem_data;
1215 Rd.uw = tmp;
1211 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
1212 {{
1213 uint32_t tmp = mem_data;
1214 Rd.uw = tmp;
1216 }}, {{EXT_ASI}}, MEM_SWAP);
1215 }}, MEM_SWAP);
1217
1218 format Trap {
1219 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1220 0x21: decode RD {
1221 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1222 if (fault)
1223 return fault;
1224 Fsr = Mem.uw | Fsr<63:32>;}});

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1242 return fault;
1243 Mem.udw = Fsr;
1244 Fsr = insertBits(Fsr,16,14,0);}});
1245 default: FailUnimpl::stfsrOther();
1246 }
1247 0x26: stqf({{fault = new FpDisabled;}});
1248 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1249 0x2D: Nop::prefetch({{ }});
1216
1217 format Trap {
1218 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1219 0x21: decode RD {
1220 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1221 if (fault)
1222 return fault;
1223 Fsr = Mem.uw | Fsr<63:32>;}});

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1241 return fault;
1242 Mem.udw = Fsr;
1243 Fsr = insertBits(Fsr,16,14,0);}});
1244 default: FailUnimpl::stfsrOther();
1245 }
1246 0x26: stqf({{fault = new FpDisabled;}});
1247 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1248 0x2D: Nop::prefetch({{ }});
1250 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1249 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}});
1251 0x32: ldqfa({{fault = new FpDisabled;}});
1252 format LoadAlt {
1253 0x33: decode EXT_ASI {
1254 //ASI_NUCLEUS
1255 0x04: FailUnimpl::lddfa_n();
1256 //ASI_NUCLEUS_LITTLE
1257 0x0C: FailUnimpl::lddfa_nl();
1258 //ASI_AS_IF_USER_PRIMARY

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1294 0x16: FailUnimpl::ldblockf_aiup();
1295 //ASI_BLOCK_AS_IF_USER_SECONDARY
1296 0x17: FailUnimpl::ldblockf_aius();
1297 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1298 0x1E: FailUnimpl::ldblockf_aiupl();
1299 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1300 0x1F: FailUnimpl::ldblockf_aiusl();
1301 //ASI_BLOCK_PRIMARY
1250 0x32: ldqfa({{fault = new FpDisabled;}});
1251 format LoadAlt {
1252 0x33: decode EXT_ASI {
1253 //ASI_NUCLEUS
1254 0x04: FailUnimpl::lddfa_n();
1255 //ASI_NUCLEUS_LITTLE
1256 0x0C: FailUnimpl::lddfa_nl();
1257 //ASI_AS_IF_USER_PRIMARY

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1293 0x16: FailUnimpl::ldblockf_aiup();
1294 //ASI_BLOCK_AS_IF_USER_SECONDARY
1295 0x17: FailUnimpl::ldblockf_aius();
1296 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1297 0x1E: FailUnimpl::ldblockf_aiupl();
1298 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1299 0x1F: FailUnimpl::ldblockf_aiusl();
1300 //ASI_BLOCK_PRIMARY
1302 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1301 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
1303 //ASI_BLOCK_SECONDARY
1304 0xF1: FailUnimpl::ldblockf_s();
1305 //ASI_BLOCK_PRIMARY_LITTLE
1306 0xF8: FailUnimpl::ldblockf_pl();
1307 //ASI_BLOCK_SECONDARY_LITTLE
1308 0xF9: FailUnimpl::ldblockf_sl();
1309 }
1310

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1377 0x16: FailUnimpl::stblockf_aiup();
1378 //ASI_BLOCK_AS_IF_USER_SECONDARY
1379 0x17: FailUnimpl::stblockf_aius();
1380 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1381 0x1E: FailUnimpl::stblockf_aiupl();
1382 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1383 0x1F: FailUnimpl::stblockf_aiusl();
1384 //ASI_BLOCK_PRIMARY
1302 //ASI_BLOCK_SECONDARY
1303 0xF1: FailUnimpl::ldblockf_s();
1304 //ASI_BLOCK_PRIMARY_LITTLE
1305 0xF8: FailUnimpl::ldblockf_pl();
1306 //ASI_BLOCK_SECONDARY_LITTLE
1307 0xF9: FailUnimpl::ldblockf_sl();
1308 }
1309

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1376 0x16: FailUnimpl::stblockf_aiup();
1377 //ASI_BLOCK_AS_IF_USER_SECONDARY
1378 0x17: FailUnimpl::stblockf_aius();
1379 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1380 0x1E: FailUnimpl::stblockf_aiupl();
1381 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1382 0x1F: FailUnimpl::stblockf_aiusl();
1383 //ASI_BLOCK_PRIMARY
1385 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1384 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1386 //ASI_BLOCK_SECONDARY
1387 0xF1: FailUnimpl::stblockf_s();
1388 //ASI_BLOCK_PRIMARY_LITTLE
1389 0xF8: FailUnimpl::stblockf_pl();
1390 //ASI_BLOCK_SECONDARY_LITTLE
1391 0xF9: FailUnimpl::stblockf_sl();
1392 }
1393

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1414 }
1415 }
1416 0x3C: CasAlt::casa({{
1417 mem_data = htog(Rs2.uw);
1418 Mem.uw = Rd.uw;}},
1419 {{
1420 uint32_t tmp = mem_data;
1421 Rd.uw = tmp;
1385 //ASI_BLOCK_SECONDARY
1386 0xF1: FailUnimpl::stblockf_s();
1387 //ASI_BLOCK_PRIMARY_LITTLE
1388 0xF8: FailUnimpl::stblockf_pl();
1389 //ASI_BLOCK_SECONDARY_LITTLE
1390 0xF9: FailUnimpl::stblockf_sl();
1391 }
1392

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1413 }
1414 }
1415 0x3C: CasAlt::casa({{
1416 mem_data = htog(Rs2.uw);
1417 Mem.uw = Rd.uw;}},
1418 {{
1419 uint32_t tmp = mem_data;
1420 Rd.uw = tmp;
1422 }}, {{EXT_ASI}}, MEM_SWAP_COND);
1421 }}, MEM_SWAP_COND);
1423 0x3D: Nop::prefetcha({{ }});
1424 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1425 Mem.udw = Rd.udw; }},
1422 0x3D: Nop::prefetcha({{ }});
1423 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1424 Mem.udw = Rd.udw; }},
1426 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND);
1425 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND);
1427 }
1428 }
1429}
1426 }
1427 }
1428}