decoder.isa (5093:7f20bc69fda5) decoder.isa (5094:10b8551e3e3f)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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308 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
309 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
310 }
311 0x28: decode RS1 {
312 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
313 //1 should cause an illegal instruction exception
314 0x02: NoPriv::rdccr({{Rd = Ccr;}});
315 0x03: NoPriv::rdasi({{Rd = Asi;}});
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 299 unchanged lines hidden (view full) ---

308 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
309 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
310 }
311 0x28: decode RS1 {
312 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
313 //1 should cause an illegal instruction exception
314 0x02: NoPriv::rdccr({{Rd = Ccr;}});
315 0x03: NoPriv::rdasi({{Rd = Asi;}});
316 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
316 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
317 0x05: NoPriv::rdpc({{
318 if(Pstate<3:>)
319 Rd = (xc->readPC())<31:0>;
320 else
321 Rd = xc->readPC();}});
322 0x06: NoPriv::rdfprs({{
323 //Wait for all fpops to finish.
324 Rd = Fprs;
325 }});
326 //7-14 should cause an illegal instruction exception
327 0x0F: decode I {
328 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
329 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
330 }
331 0x10: Priv::rdpcr({{Rd = Pcr;}});
317 0x05: NoPriv::rdpc({{
318 if(Pstate<3:>)
319 Rd = (xc->readPC())<31:0>;
320 else
321 Rd = xc->readPC();}});
322 0x06: NoPriv::rdfprs({{
323 //Wait for all fpops to finish.
324 Rd = Fprs;
325 }});
326 //7-14 should cause an illegal instruction exception
327 0x0F: decode I {
328 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
329 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
330 }
331 0x10: Priv::rdpcr({{Rd = Pcr;}});
332 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
332 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
333 //0x12 should cause an illegal instruction exception
334 0x13: NoPriv::rdgsr({{
335 fault = checkFpEnableFault(xc);
336 if (fault)
337 return fault;
338 Rd = Gsr;
339 }});
340 //0x14-0x15 should cause an illegal instruction exception
341 0x16: Priv::rdsoftint({{Rd = Softint;}});
342 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
333 //0x12 should cause an illegal instruction exception
334 0x13: NoPriv::rdgsr({{
335 fault = checkFpEnableFault(xc);
336 if (fault)
337 return fault;
338 Rd = Gsr;
339 }});
340 //0x14-0x15 should cause an illegal instruction exception
341 0x16: Priv::rdsoftint({{Rd = Softint;}});
342 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
343 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
343 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
344 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
345 0x1A: Priv::rdstrand_sts_reg({{
346 if(Pstate<2:> && !Hpstate<2:>)
347 Rd = StrandStsReg<0:>;
348 else
349 Rd = StrandStsReg;
350 }});
351 //0x1A is supposed to be reserved, but it reads the strand
352 //status register.
353 //0x1B-0x1F should cause an illegal instruction exception
354 }
355 0x29: decode RS1 {
356 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
344 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
345 0x1A: Priv::rdstrand_sts_reg({{
346 if(Pstate<2:> && !Hpstate<2:>)
347 Rd = StrandStsReg<0:>;
348 else
349 Rd = StrandStsReg;
350 }});
351 //0x1A is supposed to be reserved, but it reads the strand
352 //status register.
353 //0x1B-0x1F should cause an illegal instruction exception
354 }
355 0x29: decode RS1 {
356 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
357 0x01: HPriv::rdhprhtstate({{
358 if(Tl == 0)
359 return new IllegalInstruction;
360 Rd = Htstate;
361 }});
357 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
362 //0x02 should cause an illegal instruction exception
363 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
364 //0x04 should cause an illegal instruction exception
365 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
366 0x06: HPriv::rdhprhver({{Rd = Hver;}});
367 //0x07-0x1E should cause an illegal instruction exception
368 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
369 }
370 0x2A: decode RS1 {
358 //0x02 should cause an illegal instruction exception
359 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
360 //0x04 should cause an illegal instruction exception
361 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
362 0x06: HPriv::rdhprhver({{Rd = Hver;}});
363 //0x07-0x1E should cause an illegal instruction exception
364 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
365 }
366 0x2A: decode RS1 {
371 0x00: Priv::rdprtpc({{
372 if(Tl == 0)
373 return new IllegalInstruction;
374 Rd = Tpc;
375 }});
376 0x01: Priv::rdprtnpc({{
377 if(Tl == 0)
378 return new IllegalInstruction;
379 Rd = Tnpc;
380 }});
381 0x02: Priv::rdprtstate({{
382 if(Tl == 0)
383 return new IllegalInstruction;
384 Rd = Tstate;
385 }});
386 0x03: Priv::rdprtt({{
387 if(Tl == 0)
388 return new IllegalInstruction;
389 Rd = Tt;
390 }});
367 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
368 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
369 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
370 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
391 0x04: Priv::rdprtick({{Rd = Tick;}});
392 0x05: Priv::rdprtba({{Rd = Tba;}});
393 0x06: Priv::rdprpstate({{Rd = Pstate;}});
394 0x07: Priv::rdprtl({{Rd = Tl;}});
395 0x08: Priv::rdprpil({{Rd = Pil;}});
396 0x09: Priv::rdprcwp({{Rd = Cwp;}});
397 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
398 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});

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450 //0x01 should cause an illegal instruction exception
451 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
452 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
453 //0x04-0x05 should cause an illegal instruction exception
454 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
455 //0x07-0x0E should cause an illegal instruction exception
456 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
457 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
371 0x04: Priv::rdprtick({{Rd = Tick;}});
372 0x05: Priv::rdprtba({{Rd = Tba;}});
373 0x06: Priv::rdprpstate({{Rd = Pstate;}});
374 0x07: Priv::rdprtl({{Rd = Tl;}});
375 0x08: Priv::rdprpil({{Rd = Pil;}});
376 0x09: Priv::rdprcwp({{Rd = Cwp;}});
377 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
378 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});

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430 //0x01 should cause an illegal instruction exception
431 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
432 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
433 //0x04-0x05 should cause an illegal instruction exception
434 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
435 //0x07-0x0E should cause an illegal instruction exception
436 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
437 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
458 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
438 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
459 //0x12 should cause an illegal instruction exception
460 0x13: NoPriv::wrgsr({{
461 if(Fprs<2:> == 0 || Pstate<4:> == 0)
462 return new FpDisabled;
463 Gsr = Rs1 ^ Rs2_or_imm13;
464 }});
465 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
466 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});

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498 else
499 Otherwin = Otherwin - 1;
500
501 if(Cleanwin < NWindows - 1)
502 Cleanwin = Cleanwin + 1;
503 }});
504 }
505 0x32: decode RD {
439 //0x12 should cause an illegal instruction exception
440 0x13: NoPriv::wrgsr({{
441 if(Fprs<2:> == 0 || Pstate<4:> == 0)
442 return new FpDisabled;
443 Gsr = Rs1 ^ Rs2_or_imm13;
444 }});
445 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
446 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});

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478 else
479 Otherwin = Otherwin - 1;
480
481 if(Cleanwin < NWindows - 1)
482 Cleanwin = Cleanwin + 1;
483 }});
484 }
485 0x32: decode RD {
506 0x00: Priv::wrprtpc({{
507 if(Tl == 0)
508 return new IllegalInstruction;
509 else
510 Tpc = Rs1 ^ Rs2_or_imm13;
511 }});
512 0x01: Priv::wrprtnpc({{
513 if(Tl == 0)
514 return new IllegalInstruction;
515 else
516 Tnpc = Rs1 ^ Rs2_or_imm13;
517 }});
518 0x02: Priv::wrprtstate({{
519 if(Tl == 0)
520 return new IllegalInstruction;
521 else
522 Tstate = Rs1 ^ Rs2_or_imm13;
523 }});
524 0x03: Priv::wrprtt({{
525 if(Tl == 0)
526 return new IllegalInstruction;
527 else
528 Tt = Rs1 ^ Rs2_or_imm13;
529 }});
486 0x00: Priv::wrprtpc(
487 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
488 0x01: Priv::wrprtnpc(
489 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
490 0x02: Priv::wrprtstate(
491 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
492 0x03: Priv::wrprtt(
493 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
530 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
531 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
532 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
533 0x07: Priv::wrprtl({{
534 if(Pstate<2:> && !Hpstate<2:>)
535 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
536 else
537 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);

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549 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
550 else
551 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
552 }});
553 //0x11-0x1F should cause an illegal instruction exception
554 }
555 0x33: decode RD {
556 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
494 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
495 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
496 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
497 0x07: Priv::wrprtl({{
498 if(Pstate<2:> && !Hpstate<2:>)
499 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
500 else
501 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);

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513 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
514 else
515 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
516 }});
517 //0x11-0x1F should cause an illegal instruction exception
518 }
519 0x33: decode RD {
520 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
557 0x01: HPriv::wrhprhtstate({{
558 if(Tl == 0)
559 return new IllegalInstruction;
560 Htstate = Rs1 ^ Rs2_or_imm13;
561 }});
521 0x01: HPriv::wrhprhtstate(
522 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
562 //0x02 should cause an illegal instruction exception
563 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
564 //0x04 should cause an illegal instruction exception
565 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
566 //0x06-0x01D should cause an illegal instruction exception
567 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
568 }
569 0x34: decode OPF{

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1125 Cwp = (Cwp - 1 + NWindows) % NWindows;
1126 Rd_prev = Rs1 + Rs2_or_imm13;
1127 Cansave = Cansave + 1;
1128 Canrestore = Canrestore - 1;
1129 }
1130 }});
1131 0x3E: decode FCN {
1132 0x0: Priv::done({{
523 //0x02 should cause an illegal instruction exception
524 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
525 //0x04 should cause an illegal instruction exception
526 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
527 //0x06-0x01D should cause an illegal instruction exception
528 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
529 }
530 0x34: decode OPF{

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1086 Cwp = (Cwp - 1 + NWindows) % NWindows;
1087 Rd_prev = Rs1 + Rs2_or_imm13;
1088 Cansave = Cansave + 1;
1089 Canrestore = Canrestore - 1;
1090 }
1091 }});
1092 0x3E: decode FCN {
1093 0x0: Priv::done({{
1133 if(Tl == 0)
1134 return new IllegalInstruction;
1135
1136 Cwp = Tstate<4:0>;
1137 Pstate = Tstate<20:8>;
1138 Asi = Tstate<31:24>;
1139 Ccr = Tstate<39:32>;
1140 Gl = Tstate<42:40>;
1141 Hpstate = Htstate;
1142 NPC = Tnpc;
1143 NNPC = Tnpc + 4;
1144 Tl = Tl - 1;
1094 Cwp = Tstate<4:0>;
1095 Pstate = Tstate<20:8>;
1096 Asi = Tstate<31:24>;
1097 Ccr = Tstate<39:32>;
1098 Gl = Tstate<42:40>;
1099 Hpstate = Htstate;
1100 NPC = Tnpc;
1101 NNPC = Tnpc + 4;
1102 Tl = Tl - 1;
1145 }});
1103 }}, checkTl=true);
1146 0x1: Priv::retry({{
1104 0x1: Priv::retry({{
1147 if(Tl == 0)
1148 return new IllegalInstruction;
1149 Cwp = Tstate<4:0>;
1150 Pstate = Tstate<20:8>;
1151 Asi = Tstate<31:24>;
1152 Ccr = Tstate<39:32>;
1153 Gl = Tstate<42:40>;
1154 Hpstate = Htstate;
1155 NPC = Tpc;
1156 NNPC = Tnpc;
1157 Tl = Tl - 1;
1105 Cwp = Tstate<4:0>;
1106 Pstate = Tstate<20:8>;
1107 Asi = Tstate<31:24>;
1108 Ccr = Tstate<39:32>;
1109 Gl = Tstate<42:40>;
1110 Hpstate = Htstate;
1111 NPC = Tpc;
1112 NNPC = Tnpc;
1113 Tl = Tl - 1;
1158 }});
1114 }}, checkTl=true);
1159 }
1160 }
1161 }
1162 0x3: decode OP3 {
1163 format Load {
1164 0x00: lduw({{Rd = Mem.uw;}});
1165 0x01: ldub({{Rd = Mem.ub;}});
1166 0x02: lduh({{Rd = Mem.uhw;}});

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1116 }
1117 }
1118 0x3: decode OP3 {
1119 format Load {
1120 0x00: lduw({{Rd = Mem.uw;}});
1121 0x01: ldub({{Rd = Mem.ub;}});
1122 0x02: lduh({{Rd = Mem.uhw;}});

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