decoder.isa (4204:43daa3de387e) decoder.isa (4224:7e828583f2cb)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 1306 unchanged lines hidden (view full) ---

1315 RdLow = (Mem.tuw).a;
1316 RdHigh = (Mem.tuw).b;
1317 }});
1318 }
1319 format Store {
1320 0x04: stw({{Mem.uw = Rd.sw;}});
1321 0x05: stb({{Mem.ub = Rd.sb;}});
1322 0x06: sth({{Mem.uhw = Rd.shw;}});
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 1306 unchanged lines hidden (view full) ---

1315 RdLow = (Mem.tuw).a;
1316 RdHigh = (Mem.tuw).b;
1317 }});
1318 }
1319 format Store {
1320 0x04: stw({{Mem.uw = Rd.sw;}});
1321 0x05: stb({{Mem.ub = Rd.sb;}});
1322 0x06: sth({{Mem.uhw = Rd.shw;}});
1323 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1323 0x07: sttw({{
1324 (Mem.tuw).a = RdLow<31:0>;
1325 (Mem.tuw).b = RdHigh<31:0>;
1326 }});
1324 }
1325 format Load {
1326 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1327 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1328 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1329 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1330 }
1331 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},

--- 73 unchanged lines hidden (view full) ---

1405 RdHigh = (Mem.tuw).b;
1406 }}, {{EXT_ASI}});
1407 }
1408 }
1409 format StoreAlt {
1410 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1411 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1412 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1327 }
1328 format Load {
1329 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1330 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1331 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1332 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1333 }
1334 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},

--- 73 unchanged lines hidden (view full) ---

1408 RdHigh = (Mem.tuw).b;
1409 }}, {{EXT_ASI}});
1410 }
1411 }
1412 format StoreAlt {
1413 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1414 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1415 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1413 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1416 0x17: sttwa({{
1417 (Mem.tuw).a = RdLow<31:0>;
1418 (Mem.tuw).b = RdHigh<31:0>;
1419 }}, {{EXT_ASI}});
1414 }
1415 format LoadAlt {
1416 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1417 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1418 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1419 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1420 }
1421 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},

--- 223 unchanged lines hidden --- 		1420 }
1421 format LoadAlt {
1422 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1423 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1424 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1425 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1426 }
1427 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},

--- 223 unchanged lines hidden ---