decoder.isa (4011:e6899d7ca5b1) decoder.isa (4040:eb894f3fc168)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
475 0x0: Nop::stbar({{/*stuff*/}});
476 0x1: Nop::membar({{/*stuff*/}});
475 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
476 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;

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1163 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1164 }
1165 format Load {
1166 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1167 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1168 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1169 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1170 }
477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;

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1163 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1164 }
1165 format Load {
1166 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1167 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1168 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1169 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1170 }
1171 0x0D: LoadStore::ldstub(
1172 {{uReg0 = Mem.ub;}},
1173 {{Rd.ub = uReg0;
1174 Mem.ub = 0xFF;}});
1171 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
1172 {{
1173 uint8_t tmp = mem_data;
1174 Rd.ub = tmp;
1175 }}, MEM_SWAP);
1175 0x0E: Store::stx({{Mem.udw = Rd}});
1176 0x0E: Store::stx({{Mem.udw = Rd}});
1176 0x0F: LoadStore::swap(
1177 {{ uReg0 = Mem.uw}},
1178 {{ Mem.uw = Rd.uw;
1179 Rd.uw = uReg0;}});
1177 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
1178 {{
1179 uint32_t tmp = mem_data;
1180 Rd.uw = tmp;
1181 }}, MEM_SWAP);
1180 format LoadAlt {
1181 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1182 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1183 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1184 0x13: decode EXT_ASI {
1185 //ASI_LDTD_AIUP
1186 0x22: TwinLoad::ldtx_aiup(
1182 format LoadAlt {
1183 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1184 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1185 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1186 0x13: decode EXT_ASI {
1187 //ASI_LDTD_AIUP
1188 0x22: TwinLoad::ldtx_aiup(
1187 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1189 {{RdLow.udw = (Mem.tudw).a;
1190 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1188 //ASI_LDTD_AIUS
1189 0x23: TwinLoad::ldtx_aius(
1191 //ASI_LDTD_AIUS
1192 0x23: TwinLoad::ldtx_aius(
1190 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1193 {{RdLow.udw = (Mem.tudw).a;
1194 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1191 //ASI_QUAD_LDD
1192 0x24: TwinLoad::ldtx_quad_ldd(
1195 //ASI_QUAD_LDD
1196 0x24: TwinLoad::ldtx_quad_ldd(
1193 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1197 {{RdLow.udw = (Mem.tudw).a;
1198 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1194 //ASI_LDTX_REAL
1195 0x26: TwinLoad::ldtx_real(
1199 //ASI_LDTX_REAL
1200 0x26: TwinLoad::ldtx_real(
1196 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1197 //ASI_LDTX_N
1198 0x27: TwinLoad::ldtx_n(
1199 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1200 //ASI_LDTX_L
1201 0x2C: TwinLoad::ldtx_l(
1202 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1201 {{RdLow.udw = (Mem.tudw).a;
1202 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1203 //ASI_LDTX_N
1204 0x27: TwinLoad::ldtx_n(
1205 {{RdLow.udw = (Mem.tudw).a;
1206 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1207 //ASI_LDTX_AIUP_L
1208 0x2A: TwinLoad::ldtx_aiup_l(
1209 {{RdLow.udw = (Mem.tudw).a;
1210 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1211 //ASI_LDTX_AIUS_L
1212 0x2B: TwinLoad::ldtx_aius_l(
1213 {{RdLow.udw = (Mem.tudw).a;
1214 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1215 //ASI_LDTX_L
1216 0x2C: TwinLoad::ldtx_l(
1217 {{RdLow.udw = (Mem.tudw).a;
1218 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1203 //ASI_LDTX_REAL_L
1204 0x2E: TwinLoad::ldtx_real_l(
1219 //ASI_LDTX_REAL_L
1220 0x2E: TwinLoad::ldtx_real_l(
1205 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1221 {{RdLow.udw = (Mem.tudw).a;
1222 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1206 //ASI_LDTX_N_L
1207 0x2F: TwinLoad::ldtx_n_l(
1223 //ASI_LDTX_N_L
1224 0x2F: TwinLoad::ldtx_n_l(
1208 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1225 {{RdLow.udw = (Mem.tudw).a;
1226 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1209 //ASI_LDTX_P
1210 0xE2: TwinLoad::ldtx_p(
1227 //ASI_LDTX_P
1228 0xE2: TwinLoad::ldtx_p(
1211 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1229 {{RdLow.udw = (Mem.tudw).a;
1230 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1212 //ASI_LDTX_S
1213 0xE3: TwinLoad::ldtx_s(
1231 //ASI_LDTX_S
1232 0xE3: TwinLoad::ldtx_s(
1214 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1233 {{RdLow.udw = (Mem.tudw).a;
1234 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1235 //ASI_LDTX_PL
1236 0xEA: TwinLoad::ldtx_pl(
1237 {{RdLow.udw = (Mem.tudw).a;
1238 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1239 //ASI_LDTX_SL
1240 0xEB: TwinLoad::ldtx_sl(
1241 {{RdLow.udw = (Mem.tudw).a;
1242 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1215 default: ldtwa({{
1216 uint64_t val = Mem.udw;
1217 RdLow = val<31:0>;
1218 RdHigh = val<63:32>;
1219 }}, {{EXT_ASI}});
1220 }
1221 }
1222 format StoreAlt {
1223 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1224 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1225 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1226 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1227 }
1228 format LoadAlt {
1229 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1230 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1231 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1232 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1233 }
1243 default: ldtwa({{
1244 uint64_t val = Mem.udw;
1245 RdLow = val<31:0>;
1246 RdHigh = val<63:32>;
1247 }}, {{EXT_ASI}});
1248 }
1249 }
1250 format StoreAlt {
1251 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1252 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1253 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1254 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1255 }
1256 format LoadAlt {
1257 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1258 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1259 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1260 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1261 }
1234 0x1D: LoadStoreAlt::ldstuba(
1235 {{uReg0 = Mem.ub;}},
1236 {{Rd.ub = uReg0;
1237 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1262 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
1263 {{
1264 uint8_t tmp = mem_data;
1265 Rd.ub = tmp;
1266 }}, {{EXT_ASI}}, MEM_SWAP);
1238 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1267 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1239 0x1F: LoadStoreAlt::swapa(
1240 {{ uReg0 = Mem.uw}},
1241 {{ Mem.uw = Rd.uw;
1242 Rd.uw = uReg0;}}, {{EXT_ASI}});
1268 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
1269 {{
1270 uint32_t tmp = mem_data;
1271 Rd.uw = tmp;
1272 }}, {{EXT_ASI}}, MEM_SWAP);
1273
1243 format Trap {
1244 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1245 0x21: decode RD {
1246 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1247 if (fault)
1248 return fault;
1249 Fsr = Mem.uw | Fsr<63:32>;}});
1250 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);

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1433 0xDA: FailUnimpl::stshortf_16pl();
1434 //ASI_FL16_SECONDARY_LITTLE
1435 0xDB: FailUnimpl::stshortf_16sl();
1436 //Not an ASI which is legal with lddfa
1437 default: Trap::stdfa_bad_asi(
1438 {{fault = new DataAccessException;}});
1439 }
1440 }
1274 format Trap {
1275 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1276 0x21: decode RD {
1277 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1278 if (fault)
1279 return fault;
1280 Fsr = Mem.uw | Fsr<63:32>;}});
1281 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);

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1464 0xDA: FailUnimpl::stshortf_16pl();
1465 //ASI_FL16_SECONDARY_LITTLE
1466 0xDB: FailUnimpl::stshortf_16sl();
1467 //Not an ASI which is legal with lddfa
1468 default: Trap::stdfa_bad_asi(
1469 {{fault = new DataAccessException;}});
1470 }
1471 }
1441 0x3C: Cas::casa(
1442 {{uReg0 = Mem.uw;}},
1443 {{if(Rs2.uw == uReg0)
1444 Mem.uw = Rd.uw;
1445 else
1446 storeCond = false;
1447 Rd.uw = uReg0;}}, {{EXT_ASI}});
1472 0x3C: CasAlt::casa({{
1473 mem_data = htog(Rs2.uw);
1474 Mem.uw = Rd.uw;}},
1475 {{
1476 uint32_t tmp = mem_data;
1477 Rd.uw = tmp;
1478 }}, {{EXT_ASI}}, MEM_SWAP_COND);
1448 0x3D: Nop::prefetcha({{ }});
1479 0x3D: Nop::prefetcha({{ }});
1449 0x3E: Cas::casxa(
1450 {{uReg0 = Mem.udw;}},
1451 {{if(Rs2 == uReg0)
1452 Mem.udw = Rd;
1453 else
1454 storeCond = false;
1455 Rd = uReg0;}}, {{EXT_ASI}});
1480 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1481 Mem.udw = Rd.udw; }},
1482 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND);
1456 }
1457 }
1458}
1483 }
1484 }
1485}