decoder.isa (4005:c31dee26d855) decoder.isa (4008:ccad3906006a)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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713 //0x02 should cause an illegal instruction exception
714 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
715 //0x04 should cause an illegal instruction exception
716 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
717 //0x06-0x01D should cause an illegal instruction exception
718 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
719 }
720 0x34: decode OPF{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 704 unchanged lines hidden (view full) ---

713 //0x02 should cause an illegal instruction exception
714 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
715 //0x04 should cause an illegal instruction exception
716 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
717 //0x06-0x01D should cause an illegal instruction exception
718 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
719 }
720 0x34: decode OPF{
721 format BasicOperate{
721 format FpBasic{
722 0x01: fmovs({{
723 Frds.uw = Frs2s.uw;
724 //fsr.ftt = fsr.cexc = 0
725 Fsr &= ~(7 << 14);
726 Fsr &= ~(0x1F);
727 }});
728 0x02: fmovd({{
729 Frd.udw = Frs2.udw;

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760 0x0B: FpUnimpl::fabsq();
761 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
762 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
763 0x2B: FpUnimpl::fsqrtq();
764 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
765 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
766 0x43: FpUnimpl::faddq();
767 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
722 0x01: fmovs({{
723 Frds.uw = Frs2s.uw;
724 //fsr.ftt = fsr.cexc = 0
725 Fsr &= ~(7 << 14);
726 Fsr &= ~(0x1F);
727 }});
728 0x02: fmovd({{
729 Frd.udw = Frs2.udw;

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760 0x0B: FpUnimpl::fabsq();
761 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
762 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
763 0x2B: FpUnimpl::fsqrtq();
764 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
765 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
766 0x43: FpUnimpl::faddq();
767 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
768 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
768 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
769 0x47: FpUnimpl::fsubq();
770 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
771 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
772 0x4B: FpUnimpl::fmulq();
773 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
774 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
775 0x4F: FpUnimpl::fdivq();
776 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
777 0x6E: FpUnimpl::fdmulq();
778 0x81: fstox({{
769 0x47: FpUnimpl::fsubq();
770 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
771 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
772 0x4B: FpUnimpl::fmulq();
773 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
774 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
775 0x4F: FpUnimpl::fdivq();
776 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
777 0x6E: FpUnimpl::fdmulq();
778 0x81: fstox({{
779 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
779 Frd.sdw = static_cast<int64_t>(Frs2s.sf);
780 }});
781 0x82: fdtox({{
780 }});
781 0x82: fdtox({{
782 Frd.df = (double)static_cast<int64_t>(Frs2.df);
782 Frd.sdw = static_cast<int64_t>(Frs2.df);
783 }});
784 0x83: FpUnimpl::fqtox();
785 0x84: fxtos({{
783 }});
784 0x83: FpUnimpl::fqtox();
785 0x84: fxtos({{
786 Frds.sf = static_cast<float>((int64_t)Frs2.df);
786 Frds.sf = static_cast<float>(Frs2.sdw);
787 }});
788 0x88: fxtod({{
787 }});
788 0x88: fxtod({{
789 Frd.df = static_cast<double>((int64_t)Frs2.df);
789 Frd.df = static_cast<double>(Frs2.sdw);
790 }});
791 0x8C: FpUnimpl::fxtoq();
792 0xC4: fitos({{
790 }});
791 0x8C: FpUnimpl::fxtoq();
792 0xC4: fitos({{
793 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
793 Frds.sf = static_cast<float>(Frs2s.sw);
794 }});
795 0xC6: fdtos({{Frds.sf = Frs2.df;}});
796 0xC7: FpUnimpl::fqtos();
797 0xC8: fitod({{
794 }});
795 0xC6: fdtos({{Frds.sf = Frs2.df;}});
796 0xC7: FpUnimpl::fqtos();
797 0xC8: fitod({{
798 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
798 Frd.df = static_cast<double>(Frs2s.sw);
799 }});
800 0xC9: fstod({{Frd.df = Frs2s.sf;}});
801 0xCB: FpUnimpl::fqtod();
802 0xCC: FpUnimpl::fitoq();
803 0xCD: FpUnimpl::fstoq();
804 0xCE: FpUnimpl::fdtoq();
805 0xD1: fstoi({{
799 }});
800 0xC9: fstod({{Frd.df = Frs2s.sf;}});
801 0xCB: FpUnimpl::fqtod();
802 0xCC: FpUnimpl::fitoq();
803 0xCD: FpUnimpl::fstoq();
804 0xCE: FpUnimpl::fdtoq();
805 0xD1: fstoi({{
806 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
806 Frds.sw = static_cast<int32_t>(Frs2s.sf);
807 float t = Frds.sw;
808 if (t != Frs2s.sf)
809 Fsr = insertBits(Fsr, 4,0, 0x01);
810 Fsr |= Fsr<4:0> << 5;
807 }});
808 0xD2: fdtoi({{
811 }});
812 0xD2: fdtoi({{
809 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
813 Frds.sw = static_cast<int32_t>(Frs2.df);
814 double t = Frds.sw;
815 if (t != Frs2.df)
816 Fsr = insertBits(Fsr, 4,0, 0x01);
817 Fsr |= Fsr<4:0> << 5;
810 }});
811 0xD3: FpUnimpl::fqtoi();
812 default: FailUnimpl::fpop1();
813 }
814 }
815 0x35: decode OPF{
818 }});
819 0xD3: FpUnimpl::fqtoi();
820 default: FailUnimpl::fpop1();
821 }
822 }
823 0x35: decode OPF{
816 format BasicOperate{
824 format FpBasic{
817 0x51: fcmps({{
818 uint8_t fcc;
819 if(isnan(Frs1s) || isnan(Frs2s))
820 fcc = 3;
821 else if(Frs1s < Frs2s)
822 fcc = 1;
823 else if(Frs1s > Frs2s)
824 fcc = 2;
825 else
826 fcc = 0;
827 uint8_t firstbit = 10;
828 if(FCMPCC)
829 firstbit = FCMPCC * 2 + 30;
830 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
831 }});
832 0x52: fcmpd({{
833 uint8_t fcc;
825 0x51: fcmps({{
826 uint8_t fcc;
827 if(isnan(Frs1s) || isnan(Frs2s))
828 fcc = 3;
829 else if(Frs1s < Frs2s)
830 fcc = 1;
831 else if(Frs1s > Frs2s)
832 fcc = 2;
833 else
834 fcc = 0;
835 uint8_t firstbit = 10;
836 if(FCMPCC)
837 firstbit = FCMPCC * 2 + 30;
838 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
839 }});
840 0x52: fcmpd({{
841 uint8_t fcc;
834 if(isnan(Frs1s) || isnan(Frs2s))
842 if(isnan(Frs1) || isnan(Frs2))
835 fcc = 3;
843 fcc = 3;
836 else if(Frs1s < Frs2s)
844 else if(Frs1 < Frs2)
837 fcc = 1;
845 fcc = 1;
838 else if(Frs1s > Frs2s)
846 else if(Frs1 > Frs2)
839 fcc = 2;
840 else
841 fcc = 0;
842 uint8_t firstbit = 10;
843 if(FCMPCC)
844 firstbit = FCMPCC * 2 + 30;
845 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
846 }});

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855 fcc = 2;
856 uint8_t firstbit = 10;
857 if(FCMPCC)
858 firstbit = FCMPCC * 2 + 30;
859 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
860 }});
861 0x56: fcmped({{
862 uint8_t fcc = 0;
847 fcc = 2;
848 else
849 fcc = 0;
850 uint8_t firstbit = 10;
851 if(FCMPCC)
852 firstbit = FCMPCC * 2 + 30;
853 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
854 }});

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863 fcc = 2;
864 uint8_t firstbit = 10;
865 if(FCMPCC)
866 firstbit = FCMPCC * 2 + 30;
867 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
868 }});
869 0x56: fcmped({{
870 uint8_t fcc = 0;
863 if(isnan(Frs1s) || isnan(Frs2s))
871 if(isnan(Frs1) || isnan(Frs2))
864 fault = new FpExceptionIEEE754;
872 fault = new FpExceptionIEEE754;
865 if(Frs1s < Frs2s)
873 if(Frs1 < Frs2)
866 fcc = 1;
874 fcc = 1;
867 else if(Frs1s > Frs2s)
875 else if(Frs1 > Frs2)
868 fcc = 2;
869 uint8_t firstbit = 10;
870 if(FCMPCC)
871 firstbit = FCMPCC * 2 + 30;
872 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
873 }});
874 0x57: FpUnimpl::fcmpeq();
875 default: FailUnimpl::fpop2();

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955 0x50: FailUnimpl::fpadd16();
956 0x51: FailUnimpl::fpadd16s();
957 0x52: FailUnimpl::fpadd32();
958 0x53: FailUnimpl::fpadd32s();
959 0x54: FailUnimpl::fpsub16();
960 0x55: FailUnimpl::fpsub16s();
961 0x56: FailUnimpl::fpsub32();
962 0x57: FailUnimpl::fpsub32s();
876 fcc = 2;
877 uint8_t firstbit = 10;
878 if(FCMPCC)
879 firstbit = FCMPCC * 2 + 30;
880 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
881 }});
882 0x57: FpUnimpl::fcmpeq();
883 default: FailUnimpl::fpop2();

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963 0x50: FailUnimpl::fpadd16();
964 0x51: FailUnimpl::fpadd16s();
965 0x52: FailUnimpl::fpadd32();
966 0x53: FailUnimpl::fpadd32s();
967 0x54: FailUnimpl::fpsub16();
968 0x55: FailUnimpl::fpsub16s();
969 0x56: FailUnimpl::fpsub32();
970 0x57: FailUnimpl::fpsub32s();
963 0x60: BasicOperate::fzero({{Frd.df = 0;}});
964 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
971 0x60: FpBasic::fzero({{Frd.df = 0;}});
972 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
965 0x62: FailUnimpl::fnor();
966 0x63: FailUnimpl::fnors();
967 0x64: FailUnimpl::fandnot2();
968 0x65: FailUnimpl::fandnot2s();
973 0x62: FailUnimpl::fnor();
974 0x63: FailUnimpl::fnors();
975 0x64: FailUnimpl::fandnot2();
976 0x65: FailUnimpl::fandnot2s();
969 0x66: BasicOperate::fnot2({{
977 0x66: FpBasic::fnot2({{
970 Frd.df = (double)(~((uint64_t)Frs2.df));
971 }});
978 Frd.df = (double)(~((uint64_t)Frs2.df));
979 }});
972 0x67: BasicOperate::fnot2s({{
980 0x67: FpBasic::fnot2s({{
973 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
974 }});
975 0x68: FailUnimpl::fandnot1();
976 0x69: FailUnimpl::fandnot1s();
981 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
982 }});
983 0x68: FailUnimpl::fandnot1();
984 0x69: FailUnimpl::fandnot1s();
977 0x6A: BasicOperate::fnot1({{
985 0x6A: FpBasic::fnot1({{
978 Frd.df = (double)(~((uint64_t)Frs1.df));
979 }});
986 Frd.df = (double)(~((uint64_t)Frs1.df));
987 }});
980 0x6B: BasicOperate::fnot1s({{
988 0x6B: FpBasic::fnot1s({{
981 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
982 }});
983 0x6C: FailUnimpl::fxor();
984 0x6D: FailUnimpl::fxors();
985 0x6E: FailUnimpl::fnand();
986 0x6F: FailUnimpl::fnands();
987 0x70: FailUnimpl::fand();
988 0x71: FailUnimpl::fands();
989 0x72: FailUnimpl::fxnor();
990 0x73: FailUnimpl::fxnors();
989 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
990 }});
991 0x6C: FailUnimpl::fxor();
992 0x6D: FailUnimpl::fxors();
993 0x6E: FailUnimpl::fnand();
994 0x6F: FailUnimpl::fnands();
995 0x70: FailUnimpl::fand();
996 0x71: FailUnimpl::fands();
997 0x72: FailUnimpl::fxnor();
998 0x73: FailUnimpl::fxnors();
991 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
992 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
999 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
1000 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
993 0x76: FailUnimpl::fornot2();
994 0x77: FailUnimpl::fornot2s();
1001 0x76: FailUnimpl::fornot2();
1002 0x77: FailUnimpl::fornot2s();
995 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
996 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
1003 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
1004 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
997 0x7A: FailUnimpl::fornot1();
998 0x7B: FailUnimpl::fornot1s();
999 0x7C: FailUnimpl::for();
1000 0x7D: FailUnimpl::fors();
1005 0x7A: FailUnimpl::fornot1();
1006 0x7B: FailUnimpl::fornot1s();
1007 0x7C: FailUnimpl::for();
1008 0x7D: FailUnimpl::fors();
1001 0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1002 0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1009 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1010 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1003 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1004 0x81: FailUnimpl::siam();
1005 }
1006 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
1007 0x38: Branch::jmpl({{
1008 Addr target = Rs1 + Rs2_or_imm13;
1009 if(target & 0x3)
1010 fault = new MemAddressNotAligned;

--- 220 unchanged lines hidden (view full) ---

1231 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1232 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1233 0x1F: LoadStoreAlt::swapa(
1234 {{ uReg0 = Mem.uw}},
1235 {{ Mem.uw = Rd.uw;
1236 Rd.uw = uReg0;}}, {{EXT_ASI}});
1237 format Trap {
1238 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1011 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1012 0x81: FailUnimpl::siam();
1013 }
1014 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
1015 0x38: Branch::jmpl({{
1016 Addr target = Rs1 + Rs2_or_imm13;
1017 if(target & 0x3)
1018 fault = new MemAddressNotAligned;

--- 220 unchanged lines hidden (view full) ---

1239 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1240 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1241 0x1F: LoadStoreAlt::swapa(
1242 {{ uReg0 = Mem.uw}},
1243 {{ Mem.uw = Rd.uw;
1244 Rd.uw = uReg0;}}, {{EXT_ASI}});
1245 format Trap {
1246 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1239 0x21: decode X {
1247 0x21: decode RD {
1240 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1241 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1248 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1249 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1250 default: FailUnimpl::ldfsrOther();
1242 }
1243 0x22: ldqf({{fault = new FpDisabled;}});
1244 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1245 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1251 }
1252 0x22: ldqf({{fault = new FpDisabled;}});
1253 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1254 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1246 0x25: decode X {
1247 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1248 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1255 0x25: decode RD {
1256 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;
1257 Fsr = insertBits(Fsr,16,14,0);}});
1258 0x1: Store::stxfsr({{Mem.udw = Fsr;
1259 Fsr = insertBits(Fsr,16,14,0);}});
1260 default: FailUnimpl::stfsrOther();
1249 }
1250 0x26: stqf({{fault = new FpDisabled;}});
1251 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1252 0x2D: Nop::prefetch({{ }});
1253 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1254 0x32: ldqfa({{fault = new FpDisabled;}});
1255 format LoadAlt {
1256 0x33: decode EXT_ASI {

--- 180 unchanged lines hidden --- 		1261 }
1262 0x26: stqf({{fault = new FpDisabled;}});
1263 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1264 0x2D: Nop::prefetch({{ }});
1265 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1266 0x32: ldqfa({{fault = new FpDisabled;}});
1267 format LoadAlt {
1268 0x33: decode EXT_ASI {

--- 180 unchanged lines hidden ---